Patent application number | Description | Published |
20100124110 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device comprises: a sense amplifier circuit; a first data retaining circuit and a second data retaining circuit configured to retain data and threshold voltage information, the second data retaining circuit output the data and the threshold voltage information to the outside; and a control circuit configured to control operation. The sense amplifier circuit is configured to perform a data-read operation and a threshold-voltage-information read operation at the same time. The control circuit is configured to control read operations so that either one of the data or the threshold voltage information for which a read operation is finished earlier is output from the second data retaining circuit, and the other one of the data or the threshold voltage information for which a read operation is not finished yet is read from a memory cell array and retained in the first data retaining circuit. | 05-20-2010 |
20110069545 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - A non-volatile semiconductor storage device according to an embodiment includes: a memory cell array including an array of electrically rewritable memory cells and configured to be able to store N bits of data (where N is a natural number not less than 2) in one memory cell; and a controller operative to control read, write and erase operations of the memory cell array. The memory cell array includes a first region having a first memory cell operative to retain N bits of data, and a second region having a second memory cell operative to retain M bits of data (where M is a natural number less than N). A data structure of address data received by the controller when accessing the first memory cell is the same as a data structure of address data received from the outside when accessing the second memory cell. | 03-24-2011 |
20140053041 | NONVOLATILE SEMICONDUCTOR MEMORY SYSTEM ERROR CORRECTION CAPABILITY OF WHICH IS IMPROVED - According to one embodiment, a memory system includes a memory cell array, first error correction part, second error correction part, and third error correction part. The memory cell array includes a first storage area in which 1-bit data is stored in one memory cell, and second storage area in which data of a plurality of bits is stored in one memory cell. When data is written to the first storage area, the first error correction part generates first parity data in the row direction on the basis of the data described above. The second error correction part corrects an error of the data described above on the basis of the first parity data read from the memory cell array. The third error correction part generates second parity data in the column direction on the basis of data of a plurality of pages. | 02-20-2014 |
20150074490 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to an embodiment, a nonvolatile semiconductor memory device includes a nonvolatile memory, an ECC decoder, and a write controller. The nonvolatile memory includes a memory cell array and a buffer. The buffer is capable of storing page data read from the memory cell array and generating degeneration data by performing an exclusive OR operation on page data read from the memory cell array. The ECC decoder is capable of performing ECC decode on the degeneration data input from the nonvolatile memory and determining whether the degeneration data passes ECC decode or not. The write controller is capable of causing the nonvolatile memory to rewrite the plurality of page data when the degeneration data does not pass ECC decode. | 03-12-2015 |
Patent application number | Description | Published |
20130329621 | TERMINAL DEVICE, WIRELESS BASE STATION WIRELESSLY COMMUNICATING WITH THE SAME, AND WIRELESS COMMUNICATION SYSTEM USING TERMINAL DEVICE AND WIRELESS BASE STATION - A terminal device | 12-12-2013 |
20130336188 | WIRELESS BASE STATION AND WIRELESS COMMUNICATION SYSTEM USING THE SAME - A wireless base station ( | 12-19-2013 |
20150023447 | TRANSMITTER, TRANSMISSION METHOD USED BY THE SAME, RECEIVER FOR RECEIVING A RADIO SIGNAL FROM TRANSMITTER AND WIRELESS COMMUNICATION SYSTEM INCLUDING THE SAME - A transmitter incorporates a table (TBL1) for assigning the frame lengths of 560 μs and 600 μs to the code “0” in a binary system and assigning the frame lengths of 600 μs and 560 μs to the code “1” in the binary system. The transmitter refers to the table (TBL1) and assigns the two frame lengths of 560 μs and 600 μs and the two frame lengths of 600 μs and 560 μs to the codes “0” and “1”, respectively, in the code sequences [0,0], [0,1], [1,0] and [1,1] representing the transmission information “0” to “3” represented using the binary system, and sequentially transmits four radio signals having the assigned four frame lengths. | 01-22-2015 |
20150043467 | TRANSMITTER, TRANSMISSION METHOD USED BY THE SAME, RECEIVER FOR RECEIVING A RADIO SIGNAL FROM TRANSMITTER AND WIRELESS COMMUNICATION SYSTEM INCLUDING THE SAME - A receiver has an ID that includes three signal detection intervals (S | 02-12-2015 |
20150103709 | COMMUNICATION SYSTEM, COMMUNICATION METHOD, RADIO APPARATUS IN COMMUNICATION SYSTEM AND PROGRAM EXECUTED BY TERMINAL DEVICE IN COMMUNICATION SYSTEM - A terminal device ( | 04-16-2015 |