Patent application number | Description | Published |
20090058482 | Duty detection circuit - Semiconductor memory device with duty correction circuit includes a clock edge detector configured to generate first and second detection pulses in response to a transition timing of a common clock signal in an initial measurement operation; a duty detector configured to compare the first and second detection pulses to output comparison result signals; and a code counter configured to control the duty detector based on the comparison signals outputted from the duty detector in the initial measurement operation. | 03-05-2009 |
20090086881 | Counter with overflow prevention capability - A counter with overflow prevention capability includes a counting unit configured to count an output code in response to an input signal and an overflow preventing unit configured to control the counting unit to stop counting the output code when a current value of the output code is a maximum value but a previous value thereof is not the maximum value. | 04-02-2009 |
20090115459 | Semiconductor device and operation method thereof - A semiconductor device includes a pulse signal generating unit for generating a plurality of pulse signals each of which has a different pulse width from each other, a signal multiplexing unit for outputting one of the plurality of the pulse signals as an enable signal in response to an operating frequency of the semiconductor device, and a duty ratio detecting unit for detecting a duty ratio of external clock signals in response to the enable signal. | 05-07-2009 |
20090115467 | Semiconductor device and operation method thereof - A semiconductor memory device can optimize the layout area and current consumption based on multi-phase clock signals which are generated by dividing a source clock signal using a reset signal without a delay locked loop and a phase locked loop in order to have various phase information of low frequencies and different activation timings with a constant phase difference. | 05-07-2009 |
20090160510 | BIAS VOLTAGE GENERATION CIRCUIT AND CLOCK SYNCHRONIZING CIRCUIT - Bias voltage generator circuit and clock synchronizing circuit includes a bias unit configured to control a current in response to a bandwidth control signal, an amplification unit configured to differentially amplify an input signal in response to the current controlled by the bias unit and an output unit configured to receive an output signal of the amplification unit to output the bias voltage. | 06-25-2009 |
20090168552 | Semiconductor memory device and method for operating the same - A semiconductor memory device includes an edge detector configured to receive two pairs of complementary clocks to detect edges of the clocks, a comparator configured to compare output signals of the edge detector to detect whether clocks of the same pair have a phase difference of 180 degrees and detect whether clocks of different pairs have a phase difference of 90 degrees, a control signal generator configured to generate a control signal for controlling phases of the clocks according to an output signal of the comparator, and a phase corrector configured to correct phases of the clocks in response to the control signal. | 07-02-2009 |
20110273937 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor memory device includes an edge detector configured to receive two pairs of complementary clocks to detect edges of the clocks, a comparator configured to compare output signals of the edge detector to detect whether clocks of the same pair have a phase difference of 180 degrees and detect whether clocks of different pairs have a phase difference of 90 degrees, a control signal generator configured to generate a control signal for controlling phases of the clocks according to an output signal of the comparator, and a phase corrector configured to correct phases of the clocks in response to the control signal. | 11-10-2011 |
Patent application number | Description | Published |
20090116299 | Semiconductor memory device and method for operating the same - A semiconductor memory device is capable of generating a desired output enable signal without increasing an initial count value and bit number and generating a desired final output enable signal, without unnecessary reset operations, by reflecting CAS latency information on an external clock count value. The semiconductor memory device includes a first output enable signal generating unit configured to compare a first count value, which is obtained by counting a delay locked loop (DLL) clock, with a second clock count value, which is obtained by counting an external clock until a read command is input, and output a first output enable signal, and a final output enable signal generating unit configured to output, as a final output enable signal, one of the first output enable signal and a plurality of output enable signals generated by shifting the first output enable signal, according to a column address strobe (CAS) latency. | 05-07-2009 |
20090168546 | Semiconductor memory device and method for operating the same - A semiconductor memory device includes a first buffering unit configured to buffer a first clock for an address signal and a command to be input in synchronization with the first clock, a second buffering unit configured to buffer a second clock for a data signal to be in synchronization with the second clock to output a buffered second clock having the same frequency as the first clock, a data output circuit configured to output an internal data in response to the buffered second clock, a delay unit configured to delay the buffered second clock by a predetermined time, and a phase detector configured to detect a phase difference of an output clock of the delay unit and the output clock of the first buffering unit, and to output the detection result. | 07-02-2009 |
20090219764 | Semiconductor memory device for high-speed data input / output - Semiconductor memory device for high-speed data input/output includes a first serializer configured to partially serialize input 8-bit parallel data to output first to fourth serial data, a second serializer configured to partially serialize the first to fourth serial data to output fifth and sixth serial data and a third serializer configured to serialize the fifth and sixth serial data to output seventh serial data. | 09-03-2009 |
20090222707 | Semiconductor memory device having capability of stable initial operation - A semiconductor memory device is capable of outputting a preset logic level through an EDC pin according to an operation mode during an initial operation, and providing a stable operation according to the specification of the semiconductor memory device just after the input of a data clock (WCK). The semiconductor memory device includes an output circuit configured to output a synchronous data in response to a data clock when the data clock is enabled, and output an asynchronous data when the data clock is disabled, and a data clock detection circuit configured to control outputting the asynchronous data by checking whether the data clock is in a stable state or not. | 09-03-2009 |
20090222713 | Semiconductor device and method for operating the same - Semiconductor device includes a pad for outputting a cyclic redundancy check (CRC) data for error detection and a signal outputting unit for outputting the CRC data or a data strobe signal, which is output together with data of being output in response to a read command, through the pad according to operation modes. Method for operating a semiconductor device provided a step of outputting a CRC data for error detection through a CRC data pad and a step of outputting a data strobe signal, which is output together with data output in response to a read command, through the CRC data pad according to an operation mode. | 09-03-2009 |
Patent application number | Description | Published |
20090059693 | Semiconductor memory device - A semiconductor memory device includes: a data multiplexing unit configured to output one of a data training pattern and data transferred through a first global input/output line in response to a training control signal; and a latch unit configured to latch an output of the data multiplexing unit to apply and maintain the latched output to a second global input/output line. | 03-05-2009 |
20090116331 | Semiconductor memory device and method for operating the same - Semiconductor memory device and method for operating the same includes a phase detection unit configured to compare a phase of a first reference clock and a phase of a second divided reference clock to output a comparison result signal and a phase control and division unit configured to generate the second divided reference clock by dividing a second reference clock by a predetermined ratio according to the comparison result signal outputted from the phase detection unit and adjusting a phase of the second reference clock. | 05-07-2009 |
20090119533 | Digital delay locked loop circuit using mode register set - A semiconductor memory device includes a mode register set for establishing information on a delay time, a delay time calculator for calculating an I/O path delay time of a data clock on a basis of a unit period of a system clock, and a delay locked clock generator for reflecting in the data clock a value of subtracting an output of the delay time calculator from the information established in the mode register set. | 05-07-2009 |
20120210079 | SEMICONDUCTOR MEMORY DEVICE FOR TRANSFERRING DATA AT HIGH SPEED - A semiconductor memory device includes: a data multiplexing unit configured to output one of a data training pattern and data transferred through a first global input/output line in response to a training control signal; and a latch unit configured to latch an output of the data multiplexing unit to apply and maintain the latched output to a second global input/output line. | 08-16-2012 |
20120284470 | SEMICONDUCTOR MEMORY DEVICE WITH HIGH-SPEED DATA TRANSMISSION CAPABILITY, SYSTEM HAVING THE SAME, AND METHOD FOR OPERATING THE SAME - Semiconductor memory device with high-speed data transmission capability, system having the same includes a plurality of address input circuits and a plurality of data output circuits and a training driver configured to distribute address information input through the plurality of address input circuits together with a data loading signal for a read training, and generate data training patterns to be output through the plurality of data output circuits. | 11-08-2012 |