Patent application number | Description | Published |
20080284025 | Electrically Conductive Line - The invention includes an electrically conductive line, methods of forming electrically conductive lines, and methods of reducing titanium silicide agglomeration in the fabrication of titanium silicide over polysilicon transistor gate lines. In one implementation, a method of forming an electrically conductive line includes providing a silicon-comprising layer over a substrate. An electrically conductive layer is formed over the silicon-comprising layer. An MSi | 11-20-2008 |
20090035938 | Methods of Forming CoSi2, Methods of Forming Field Effect Transistors, and Methods of Forming Conductive Contacts - The invention included to methods of forming CoSi | 02-05-2009 |
20090152629 | METHODS OF SELECTIVELY OXIDIZING SEMICONDUCTOR STRUCTURES, AND STRUCTURES RESULTING THEREFROM - Methods for selectively oxidizing a semiconductor structure include generating a gas cluster ion beam comprising an oxidizing source gas, directing the gas cluster ion beam to a region of a substrate adjacent a conductive line and exposing the region to the gas cluster ion beam including an oxidizing matter. Utilizing the gas cluster ion beam enables selective oxidation of a targeted region at temperatures substantially lower than those of typical oxidation processes thus, reducing or eliminating oxidation of the conductive line. Semiconductor devices including transistors formed using such methods are also disclosed. | 06-18-2009 |
20090294831 | Semiconductor Constructions, Methods Of Forming Transistor Gates, And Methods Of Forming NAND Cell Units - Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at least some portions of the different types of gates. FET and charge storage transistor gate stacks may be formed. The gate stacks may each include a gate material, an insulative material, and a sacrificial material. The sacrificial material is removed from the FET and charge storage transistor gate stacks. The insulative material of the FET gate stacks is etched through. A conductive material is formed over the FET gate stacks and over the charge storage transistor gate stacks. The conductive material physically contacts the gate material of the FET gate stacks, and is separated from the gate material of the charge storage transistor gate stacks by the insulative material remaining in the charge storage transistor gate stacks. Some embodiments include gate structures. | 12-03-2009 |
20100244158 | SEMICONDUCTOR STRUCTURES RESULTING FROM SELECTIVE OXIDATION - Methods for selectively oxidizing a semiconductor structure include generating a gas cluster ion beam comprising an oxidizing source gas, directing the gas cluster ion beam to a region of a substrate adjacent a conductive line and exposing the region to the gas cluster ion beam including an oxidizing matter. Utilizing the gas cluster ion beam enables selective oxidation of a targeted region at temperatures substantially lower than those of typical oxidation processes thus, reducing or eliminating oxidation of the conductive line. Semiconductor devices including transistors formed using such methods are also disclosed. | 09-30-2010 |
20110057292 | CAPACITORS AND INTERCONNECTS INCLUDING AT LEAST TWO PORTIONS OF A METAL NITRIDE MATERIAL, METHODS OF FORMING SUCH STRUCTURES, AND SEMICONDUCTOR DEVICES INCLUDING SUCH STRUCTURES - Metal-insulator-metal capacitors with a bottom electrode including at least two portions of a metal nitride material. At least one of the portions of the metal nitride material includes a different material than another portion. Interconnects including at least two portions of a metal nitride material are also disclosed, at least one of the portions of the metal nitride material are formed from a different material than another portion of the metal nitride material. Methods for fabricating such MIM capacitors and interconnects are also disclosed, as are semiconductor devices including such MIM capacitors and interconnects. | 03-10-2011 |
20110068378 | SEMICONDUCTOR DEVICES AND METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING DIFFUSION REGIONS OF REDUCED WIDTH - Semiconductor devices and methods for forming semiconductor devices are provided, including semiconductor devices that comprise one or more diffusion region in a semiconductor, the one or more diffusion regions being adjacent to a gate formed adjacent to a surface of the semiconductor (e.g., a semiconductor substrate). The one or more diffusion regions comprise a first width at a depth below the surface of the semiconductor and a second width near the surface of the semiconductor, the second width of at the one or more diffusion regions being less than about 40% greater than the first width. | 03-24-2011 |
20110095357 | Semiconductor Constructions, Methods Of Forming Transistor Gates, And Methods Of Forming NAND Cell Units - Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at least some portions of the different types of gates. FET and charge storage transistor gate stacks may be formed. The gate stacks may each include a gate material, an insulative material, and a sacrificial material. The sacrificial material is removed from the FET and charge storage transistor gate stacks. The insulative material of the FET gate stacks is etched through. A conductive material is formed over the FET gate stacks and over the charge storage transistor gate stacks. The conductive material physically contacts the gate material of the FET gate stacks, and is separated from the gate material of the charge storage transistor gate stacks by the insulative material remaining in the charge storage transistor gate stacks. Some embodiments include gate structures. | 04-28-2011 |
20110227071 | Semiconductor Constructions, Semiconductor Processing Methods, And Methods Of Forming Isolation Structures - Some embodiments include methods of forming isolation structures. A semiconductor base may be provided to have a crystalline semiconductor material projection between a pair of openings. SOD material (such as, for example, polysilazane) may be flowed within said openings to fill the openings. After the openings are filled with the SOD material, one or more dopant species may be implanted into the projection to amorphize the crystalline semiconductor material within an upper portion of said projection. The SOD material may then be annealed at a temperature of at least about 400° C. to form isolation structures. Some embodiments include semiconductor constructions that include a semiconductor material base having a projection between a pair of openings. The projection may have an upper region over a lower region, with the upper region being at least 75% amorphous, and with the lower region being entirely crystalline. | 09-22-2011 |
20110269288 | Methods of Forming CoSi2, Methods of Forming Field Effect Transistors, and Methods of Forming Conductive Contacts - The invention included to methods of forming CoSi | 11-03-2011 |
20110291147 | OHMIC CONTACTS FOR SEMICONDUCTOR STRUCTURES - A composition and method for formation of ohmic contacts on a semiconductor structure are provided. The composition includes a TiAl | 12-01-2011 |
20110315543 | FORMING MEMORY USING HIGH POWER IMPULSE MAGNETRON SPUTTERING - Forming memory using high power impulse magnetron sputtering is described herein. One or more method embodiments include forming a resistive memory material on a structure using high power impulse magnetron sputtering (HIPIMS), wherein the resistive memory material is formed on the structure in an environment having a temperature of approximately 400 degrees Celsius or less. | 12-29-2011 |
20120012914 | Semiconductor Constructions, and Methods of Forming Semiconductor Constructions - The invention includes methods of utilizing compositions containing iridium and tantalum in semiconductor constructions, and includes semiconductor constructions comprising compositions containing iridium and tantalum. The compositions containing iridium and tantalum can be utilized as barrier materials, and in some aspects can be utilized as barriers to copper diffusion. | 01-19-2012 |
20120108042 | Methods Of Forming Doped Regions In Semiconductor Substrates - Some embodiments include methods of forming one or more doped regions in a semiconductor substrate. Plasma doping may be used to form a first dopant to a first depth within the substrate. The first dopant may then be impacted with a second dopant to knock the first dopant to a second depth within the substrate. In some embodiments the first dopant is p-type (such as boron) and the second dopant is neutral type (such as germanium). In some embodiments the second dopant is heavier than the first dopant. | 05-03-2012 |
20120154919 | APPARATUSES AND DEVICES FOR ABSORBING ELECTROMAGNETIC RADIATION, AND METHODS OF FORMING THE APPARATUSES AND DEVICES - Photonic nanostructures, light absorbing apparatuses, and devices are provided. The photonic nanostructures include a plurality of photonic nanobars configured to collectively absorb light over an excitation wavelength range. At least two of the photonic nanobars of the plurality have lengths that are different from one another. Each photonic nanobar of the plurality has a substantially small width and a substantially small height relative to the different lengths. A method for forming such may comprise forming a plurality of first photonic nanobars comprising a width and a height that are smaller than a length of the plurality of first photonic nanobars, and forming a plurality of second photonic nanobars comprising a width and a height that are smaller than a length of the second photonic nanobar, wherein the lengths of the plurality of first photonic nanobars and the lengths of the plurality of second photonic nanobars are different from one another. | 06-21-2012 |
20120329231 | Semiconductor Processing Methods, And Methods Of Forming Isolation Structures - Some embodiments include methods of forming isolation structures. A semiconductor base may be provided to have a crystalline semiconductor material projection between a pair of openings. SOD material (such as, for example, polysilazane) may be flowed within said openings to fill the openings. After the openings are filled with the SOD material, one or more dopant species may be implanted into the projection to amorphize the crystalline semiconductor material within an upper portion of said projection. The SOD material may then be annealed at a temperature of at least about 400° C. to form isolation structures. Some embodiments include semiconductor constructions that include a semiconductor material base having a projection between a pair of openings. The projection may have an upper region over a lower region, with the upper region being at least 75% amorphous, and with the lower region being entirely crystalline. | 12-27-2012 |
20120329258 | METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING DIFFUSION REGIONS OF REDUCED WIDTH - Semiconductor devices and methods for forming semiconductor devices are provided, including semiconductor devices that comprise one or more diffusion region in a semiconductor, the one or more diffusion regions being adjacent to a gate formed adjacent to a surface of the semiconductor (e.g., a semiconductor substrate). The one or more diffusion regions comprise a first width at a depth below the surface of the semiconductor and a second width near the surface of the semiconductor, the second width of the one or more diffusion regions being less than about 40% greater than the first width. | 12-27-2012 |
20130012013 | Methods Of Forming Transistor Gates - Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at least some portions of the different types of gates. FET and charge storage transistor gate stacks may be formed. The gate stacks may each include a gate material, an insulative material, and a sacrificial material. The sacrificial material is removed from the FET and charge storage transistor gate stacks. The insulative material of the FET gate stacks is etched through. A conductive material is formed over the FET gate stacks and over the charge storage transistor gate stacks. The conductive material physically contacts the gate material of the FET gate stacks, and is separated from the gate material of the charge storage transistor gate stacks by the insulative material remaining in the charge storage transistor gate stacks. Some embodiments include gate structures. | 01-10-2013 |
20130072006 | Methods of Forming Doped Regions in Semiconductor Substrates - Some embodiments include methods of forming one or more doped regions in a semiconductor substrate. Plasma doping may be used to form a first dopant to a first depth within the substrate. The first dopant may then be impacted with a second dopant to knock the first dopant to a second depth within the substrate. In some embodiments the first dopant is p-type (such as boron) and the second dopant is neutral type (such as germanium). In some embodiments the second dopant is heavier than the first dopant. | 03-21-2013 |
20130193394 | INCORPORATION OF OXYGEN INTO MEMORY CELLS - Electronic apparatus, systems, and methods include a resistive random access memory cell having an oxygen gradient in a variable resistive region of the resistive random access memory cell and methods of forming the resistive random access memory cell. Oxygen can be incorporated into the resistive random access memory cell by ion implantation. Additional apparatus, systems, and methods are disclosed. | 08-01-2013 |
20130288466 | Methods of Forming Doped Regions in Semiconductor Substrates - Some embodiments include methods of forming one or more doped regions in a semiconductor substrate. Plasma doping may be used to form a first dopant to a first depth within the substrate. The first dopant may then be impacted with a second dopant to knock the first dopant to a second depth within the substrate. In some embodiments the first dopant is p-type (such as boron) and the second dopant is neutral type (such as germanium). In some embodiments the second dopant is heavier than the first dopant. | 10-31-2013 |
20140027883 | INTERCONNECTS AND SEMICONDUCTOR DEVICES INCLUDING AT LEAST TWO PORTIONS OF A METAL NITRIDE MATERIAL AND METHODS OF FABRICATION - Metal-insulator-metal capacitors with a bottom electrode including at least two portions of a metal nitride material. At least one of the portions of the metal nitride material includes a different material than another portion. Interconnects including at least two portions of a metal nitride material are also disclosed, at least one of the portions of the metal nitride material are formed from a different material than another portion of the metal nitride material. Methods for fabricating such MIM capacitors and interconnects are also disclosed, as are semiconductor devices including such MIM capacitors and interconnects. | 01-30-2014 |
20140054677 | Arrays Comprising Vertically-Oriented Transistors, Integrated Circuitry Comprising A Conductive Line Buried In Silicon-Comprising Semiconductor Material, Methods Of Forming A Plurality Of Conductive Lines Buried In Silicon-Comprising Semiconductor Material, And Methods Of Forming An Array Comprising Vertically-Oriented Transistors - An array includes vertically-oriented transistors, rows of access lines, and columns of data/sense lines. Individual of the rows include an access line interconnecting transistors in that row. Individual of the columns include a data/sense line interconnecting transistors in that column. The data/sense line has silicon-comprising semiconductor material between the transistors in that column that is conductively-doped n-type with at least one of As and Sb. The conductively-doped semiconductor material of the data/sense line includes a conductivity-neutral dopant between the transistors in that column. Methods are disclosed. | 02-27-2014 |
20140054678 | N-type Field Effect Transistors, Arrays Comprising N-type Vertically-Oriented Transistors, Methods Of Forming An N-type Field Effect Transistor, And Methods Of Forming An Array Comprising Vertically-Oriented N-type Transistors - An n-type field effect transistor includes silicon-comprising semiconductor material comprising a pair of source/drain regions having a channel region there-between. At least one of the source/drain regions is conductively doped n-type with at least one of As and P. A conductivity-neutral dopant is in the silicon-comprising semiconductor material in at least one of the channel region and the at least one source/drain region. A gate construction is operatively proximate the channel region. Methods are disclosed. | 02-27-2014 |
20140159172 | Transistors, Semiconductor Devices, and electronic devices including transistor gates with conductive elements including cobalt silicide - A method for fabricating a transistor gate with a conductive element that includes cobalt silicide includes use of a sacrificial material as a place-holder between sidewall spacers of the transistor gate until after high temperature processes, such as the fabrication of raised source and drain regions, have been completed. In addition, semiconductor devices (e.g., DRAM devices and NAND flash memory devices) with transistor gates that include cobalt silicide in their conductive elements are also disclosed, as are transistors with raised source and drain regions and cobalt silicide in the transistor gates thereof. Intermediate semiconductor device structures that include transistor gates with sacrificial material or a gap between upper portions of sidewall spacers are also disclosed. | 06-12-2014 |
20140206183 | Semiconductor Constructions, Methods Of Forming Transistor Gates, And Methods Of Forming NAND Cell Units - Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at least some portions of the different types of gates. FET and charge storage transistor gate stacks may be formed. The gate stacks may each include a gate material, an insulative material, and a sacrificial material. The sacrificial material is removed from the FET and charge storage transistor gate stacks. The insulative material of the FET gate stacks is etched through. A conductive material is formed over the FET gate stacks and over the charge storage transistor gate stacks. The conductive material physically contacts the gate material of the FET gate stacks, and is separated from the gate material of the charge storage transistor gate stacks by the insulative material remaining in the charge storage transistor gate stacks. Some embodiments include gate structures. | 07-24-2014 |
20140234996 | OHMIC CONTACTS FOR SEMICONDUCTOR STRUCTURES - A composition and method for formation of ohmic contacts on a semiconductor structure are provided. The composition includes a TiAl | 08-21-2014 |