Patent application number | Description | Published |
20100185876 | KEYBOARD-INPUT INFORMATION-SECURITY APPARATUS AND METHOD - A keyboard-input information-security apparatus and method are provided. The apparatus includes an interrupt-descriptor table for storing a list of addresses of functions for handling interrupts, and storing an address of a secure input interrupt-service routine at a specific location in an address area for an operating-system input interrupt-service routine supported by an operating system; a secure input-device driver for changing keyboard-interrupt-vector information to invoke the address of the secure input interrupt-service routine when a keyboard interrupt is generated by a keyboard, and receiving and encoding data input via the keyboard based on the address of the secure input interrupt-service routine; and a secure input unit for delivering the encoded data from the secure input-device driver to an application program, thereby providing higher-level security than a conventional keyboard-security scheme, and particularly, effectively blocking a port-polling attack or an action trying to change a setting in a debug register. | 07-22-2010 |
20100308865 | SEMICONDUCTOR DEVICE - A semiconductor device includes a buffer unit configured to include first and second buffers, connected to each other in a cross-coupled manner, to receive a reference voltage and to buffer an input signal applied to the first and second buffers based on the reference voltage to drive an output terminal with a current-driving capacity; and a drive power adjustor configured to adjust the current-driving capacity depending on a level of a power supply voltage applied to the buffering unit. | 12-09-2010 |
20110027535 | ANISOTROPIC PARTICLE-ARRANGED STRUCTURE AND METHOD OF MANUFACTURING THE SAME - Provided are a light, thin, short and small, and multi-functional anisotropic particle-arranged structure including two electrodes having fine pitches that are repeatedly compressed to be connected to external elements, and a method of manufacturing the anisotropic particle-arranged structure. The anisotropic particle-arranged structure includes an elastic polymer layer, and elastic conductors or elastic thermal conductors formed in the elastic polymer layer so that upper and lower portions of the elastic conductors or elastic thermal conductors are exposed. | 02-03-2011 |
20110156771 | SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor device includes: an internal clock signal generation unit configured to receive an external clock signal and to generate an internal clock signal in response to a control signal; and a monitoring unit configured to monitor environmental elements reflected in a circuit response to the control signal. | 06-30-2011 |
20110156778 | INTERNAL CLOCK SIGNAL GENERATOR AND OPERATING METHOD THEREOF - An internal clock signal generation circuit is capable of controlling a unit delay time depending on a frequency of an external clock signal. The internal clock signal generation circuit includes an internal clock signal generation unit configured to generate an internal clock signal corresponding to a plurality of unit delay cells enabled in response to a control signal, and a unit delay time control unit configured to detect a frequency of an external clock signal and control a unit delay time of each of the plurality of unit delay cells. | 06-30-2011 |
20110187432 | SEMICONDUCTOR DEVICE - A semiconductor device including a common delay circuit configured to delay an input signal in response to a delay control code to output a first delayed input signal and a second delayed input signal; a first delay circuit configured to delay the first delayed input signal in response to the delay control code and to output a first output signal; and a second delay circuit configured to delay the second delayed input signal in response to the delay control code and to output a second output signal. | 08-04-2011 |
20120008435 | DELAY LOCKED LOOP - A delay locked loop includes a closed loop circuit configured to generate preliminary delay information, a control unit configured to update the preliminary delay information into delay information in response to a control signal, and a first delay unit configured to delay an input clock signal by a first delay value determined by the delay information and generate an output clock signal. | 01-12-2012 |
20130038368 | SEMICONDUCTOR DEVICE - A semiconductor device including a common delay circuit configured to delay an input signal in response to a delay control code to output a first delayed input signal and a second delayed input signal; a first delay circuit configured to delay the first delayed input signal in response to the delay control code and to output a first output signal; and a second delay circuit configured to delay the second delayed input signal in response to the delay control code and to output a second output signal. | 02-14-2013 |
20130120042 | DELAY LOCKED LOOP - A delay locked loop includes a closed loop circuit configured to generate preliminary delay information, a control unit configured to update the preliminary delay information into delay information in response to a control signal, and a first delay unit configured to delay an input clock signal by a first delay value determined by the delay information and generate an output clock signal. | 05-16-2013 |
20130200531 | Circuit Board, Method for Fabricating the Same and Semiconductor Package Using the Same - A circuit board is provided including a core insulation film having a thickness and including a first surface and an opposite second surface, an upper stack structure and a lower stack structure. The upper stack structure has a thickness and has an upper conductive pattern having a thickness and an overlying upper insulation film stacked on the first surface of the core insulation film. The lower stack structure has a thickness and has a lower conductive pattern having a thickness and an overlying lower insulation film stacked on the second surface of the core insulation film. A ratio P of a sum of the thicknesses of the upper conductive pattern and the lower conductive pattern to a sum of the thicknesses of the core insulation film, the upper stack structure and the lower stack structure is in a range from about 0.05 to about 0.2. | 08-08-2013 |
20130230104 | METHOD AND APPARATUS FOR ENCODING/DECODING IMAGES USING THE EFFECTIVE SELECTION OF AN INTRA-PREDICTION MODE GROUP - A video encoding/decoding method and apparatus select a prediction mode set based on neighboring pixels and, in some embodiments, obviate the need to encode additional information for selecting a prediction mode set and thereby improve the performance of compression. | 09-05-2013 |