Patent application number | Description | Published |
20080236617 | USE OF DILUTE HYDROCHLORIC ACID IN ADVANCED INTERCONNECT CONTACT CLEAN IN NICKEL SEMICONDUCTOR TECHNOLOGIES - A method for cleaning oxide from the interconnects of a semiconductor that are comprised of nickel (Ni) silicide or nickel-silicide alloys where nickel is the primary metallic component is disclosed. The cleaning comprises performing an SC1 cycle, exposing the wafer comprising a NiSi contact to an SC1 solution. This removes oxygen atoms from the silicon oxide of the nickel silicide. Next, a rinse cycle is performed on the wafer to remove the SC1 solution. Finally, an HCl cycle is performed. During this cycle, the wafer comprising an NiSi contact is introduced to an HCl solution, removing oxygen atoms from the nickel oxide of the NiSi. The method of the present invention provides for lower contact resistance of NiSi semiconductor devices, facilitating semiconductor devices that have the benefits of miniaturization allowed by the NiSi technology, and higher performance due to the reduced contact resistance. | 10-02-2008 |
20080237869 | STRUCTURE AND METHOD FOR LOW RESISTANCE INTERCONNECTIONS - A method of forming an interconnection in a semiconductor device includes forming a first liner in a dielectric layer therein; depositing a tungsten filler on top of the first liner; performing chemical mechanical planarization (CMP) to smooth out and remove the first liner and tungsten filler from the semiconductor's exposed surface; selectively removing the first liner and tungsten filler in the via; wherein the selective removing results in the first liner and the tungsten filler being removed in an upper region of the via; forming a second liner in the upper region of the via and tungsten filler; selectively removing the second liner from the tungsten filler; forming a copper seed layer on top of the tungsten filler; depositing a copper filler on top of the copper seed layer; and performing chemical CMP to smooth out and remove the second liner and copper filler from the semiconductor's exposed surface. | 10-02-2008 |
20090096108 | STRUCTURE AND METHODS OF FORMING CONTACT STRUCTURES - Methods and a structure. A method of forming contact structure includes depositing a silicide layer onto a substrate; depositing an electrically insulating layer over a first surface of the silicide layer; forming a via through the insulating layer extending to the first surface; depositing an electrically conductive layer covering a bottom and at least one vertical wall of the via; removing the conductive layer from the bottom; and filling the via with aluminum directly contacting the silicide layer. A structure includes: a silicide layer disposed on a substrate; an electrically insulating layer disposed over the silicide layer; an aluminum plug extending through the insulating layer and directly contacting the silicide layer; and an electrically conductive layer disposed between the plug and the insulating layer. Also included is a method where an aluminum layer grows selectively from a silicide layer and at least one sidewall of a trench. | 04-16-2009 |
20090176351 | STRUCTURE AND METHOD TO IMPROVE MOSFET RELIABILITY - A method embodiment deposits a dielectric layer over a transistor and then implants a gettering agent into the dielectric layer. The insulating layer into which the gettering agent is implanted comprises a single continuous insulating layer and is the insulating layer that borders the next layer of metallization. After this dielectric layer is formed, standard contacts (tungsten) are formed through the insulating layer to the source, drain, gate, etc. of the transistor. Additionally, reactive ion etching of the contacts is performed. The reactive ion etching process can create mobile ions; however, the gettering agent traps the mobile ions and prevents the mobile ions from contaminating the transistor. | 07-09-2009 |
20110079851 | SPLIT LEVEL SHALLOW TRENCH ISOLATION FOR AREA EFFICIENT BODY CONTACTS IN SOI MOSFETS - Disclosed is an SOI device on a bulk silicon layer which has an FET region, a body contact region and an STI region. The FET region is made of an SOI layer and an overlying gate. The STI region includes a first STI layer separating the SOI device from an adjacent SOI device. The body contact region includes an extension of the SOI layer, a second STI layer on the extension and a body contact in contact with the extension. The first and second STI layers are contiguous and of different thicknesses so as to form a split level STI. | 04-07-2011 |
20110318897 | Method of Forming a Shallow Trench Isolation Embedded Polysilicon Resistor - Forming a polysilicon embedded resistor within the shallow trench isolations separating the active area of two adjacent devices, minimizing the electrical interaction between two devices and reducing the capacitive coupling or leakage therebetween. The precision polysilicon resistor is formed independently from the formation of gate electrodes by creating a recess region within the STI region when the polysilicon resistor is embedded within the STI recess region. The polysilicon resistor is decoupled from the gate electrode, making it immune to gate electrode related processes. The method forms the polysilicon resistor following the formation of STIs but before the formation of the p-well and n-well implants. In another embodiment the resistor is formed following the formation of the STIs but after the formation of the well implants. | 12-29-2011 |
20120119307 | SELF-ALIGNED CONTACT EMPLOYING A DIELECTRIC METAL OXIDE SPACER - A dielectric liner is formed on sidewalls of a gate stack and a lower contact-level dielectric material layer is deposited on the dielectric liner and planarized. The dielectric liner is recessed relative to the top surface of the lower contact-level dielectric material layer and the top surface of the gate stack. A dielectric metal oxide layer is deposited and planarized to form a dielectric metal oxide spacer that surrounds an upper portion of the gate stack. The dielectric metal oxide layer has a top surface that is coplanar with a top surface of the planarized lower contact-level dielectric material layer. Optionally, the conductive material in the gate stack may be replaced. After deposition of at least one upper contact-level dielectric material layer, at least one via hole extending to a semiconductor substrate is formed employing the dielectric metal oxide spacer as a self-aligning structure. | 05-17-2012 |
20120129312 | METHOD OF FORMING E-FUSE IN REPLACEMENT METAL GATE MANUFACTURING PROCESS - Embodiment of the present invention provides a method of forming electronic fuse or commonly known as e-fuse. The method includes forming a polysilicon structure and a field-effect-transistor (FET) structure together on top of a common semiconductor substrate, the FET structure having a sacrificial gate electrode; implanting at least one dopant into the polysilicon structure to create a doped polysilicon layer in at least a top portion of the polysilicon structure; subjecting the polysilicon structure and the FET structure to a reactive-ion-etching (RIE) process, the RIE process selectively removing the sacrificial gate electrode of the FET structure while the doped polysilicon layer being substantially unaffected by the RIE process; and converting the polysilicon structure including the doped polysilicon layer into a silicide to form the electronic fuse. | 05-24-2012 |
20120139061 | Self-Aligned Contact For Replacement Gate Devices - A conductive top surface of a replacement gate stack is recessed relative to a top surface of a planarization dielectric layer by at least one etch. A dielectric capping layer is deposited over the planarization dielectric layer and the top surface of the replacement gate stack so that the top surface of a portion of the dielectric capping layer over the replacement gate stack is vertically recessed relative to another portion of the dielectric layer above the planarization dielectric layer. The vertical offset of the dielectric capping layer can be employed in conjunction with selective via etch processes to form a self-aligned contact structure. | 06-07-2012 |
20120153482 | STRUCTURE AND METHODS OF FORMING CONTACT STRUCTURES - A contact structure and a method of forming the contact structure. The structure includes: a silicide layer on and in direct physical contact with a top substrate surface of a substrate; an electrically insulating layer on the substrate; and an aluminum plug within the insulating layer. The aluminum plug has a thickness not exceeding 25 nanometers in a direction perpendicular to the top substrate surface. The aluminum plug extends from a top surface of the silicide layer to a top surface of the insulating layer. The aluminum plug is in direct physical contact with the top surface of the silicide layer and is in direct physical contact with the silicide layer. The method includes: forming the silicide layer on and in direct physical contact with the top substrate surface of the substrate; forming the electrically insulating layer on the substrate; and forming the aluminum plug within the insulating layer. | 06-21-2012 |
20120175711 | Self-Aligned Contacts for High k/Metal Gate Process Flow - A semiconductor structure is provided that includes a semiconductor substrate having a plurality of gate stacks located on a surface of the semiconductor substrate. Each gate stack includes, from bottom to top, a high k gate dielectric layer, a work function metal layer and a conductive metal. A spacer is located on sidewalls of each gate stack and a self-aligned dielectric liner is present on an upper surface of each spacer. A bottom surface of each self-aligned dielectric liner is present on an upper surface of a semiconductor metal alloy. A contact metal is located between neighboring gate stacks and is separated from each gate stack by the self-aligned dielectric liner. The structure also includes another contact metal having a portion that is located on and in direct contact with an upper surface of the contact metal and another portion that is located on and in direct contact with the conductive metal of one of the gate stacks. Methods of forming the semiconductor structure using a replacement gate and a non-replacement gate scheme are also disclosed. | 07-12-2012 |
20120256267 | Electrical Fuse Formed By Replacement Metal Gate Process - A method is provided for fabricating an electrical fuse and a field effect transistor having a metal gate which includes removing material from first and second openings in a dielectric region overlying a substrate, wherein the first opening is aligned with an active semiconductor region of the substrate, and the second opening is aligned with an isolation region of the substrate, and the active semiconductor region including a source region and a drain region adjacent edges of the first opening. An electrical fuse can be formed which has a fuse element filling the second opening, the fuse element being a monolithic region of a single conductive material being a metal or a conductive compound of a metal. A metal gate can be formed which extends within the first opening to define a field effect transistor (“FET”) which includes the metal gate and the active semiconductor region. | 10-11-2012 |
20120306093 | CONVERTING METAL MASK TO METAL-OXIDE ETCH STOP LAYER AND RELATED SEMICONDUCTOR STRUCTURE - A method includes providing a semiconductor structure including a plurality of devices; depositing a nitride cap over the semiconductor structure; forming an aluminum mask over the nitride cap, the aluminum mask including a plurality of first openings; converting the aluminum mask to an aluminum oxide etch stop layer; and performing middle-of-line fabrication processing, leaving the aluminum oxide etch stop layer in place. A semiconductor structure includes a plurality of devices on a substrate; a nitride cap over the plurality of devices; an aluminum oxide etch stop layer over the nitride cap; an inter-level dielectric (ILD) over the aluminum oxide etch stop layer; and a plurality of contacts extending through the ILD, the aluminum oxide etch stop layer and the nitride cap to the plurality of devices. | 12-06-2012 |
20130015580 | REPLACEMENT METAL GATE STRUCTURE AND METHODS OF MANUFACTUREAANM JAIN; SAMEER HAACI BeaconAAST NYAACO USAAGP JAIN; SAMEER H Beacon NY USAANM Johnson; Jeffrey B.AACI Essex JunctionAAST VTAACO USAAGP Johnson; Jeffrey B. Essex Junction VT USAANM Li; YingAACI NewburghAAST NYAACO USAAGP Li; Ying Newburgh NY USAANM Nayfeh; Hasan M.AACI PoughkeepsieAAST NYAACO USAAGP Nayfeh; Hasan M. Poughkeepsie NY USAANM Ramachandran; RavikumarAACI PleasantvilleAAST NYAACO USAAGP Ramachandran; Ravikumar Pleasantville NY US - A replacement metal gate structure and methods of manufacturing the same is provided. The method includes forming at least one trench structure and forming a liner of high-k dielectric material in the at least one trench structure. The method further includes adjusting a height of the liner of high-k dielectric material. The method further includes forming at least one workfunction metal over the liner, and forming a metal gate structure in the at least one trench structure, over the at least one workfunction metal and the liner of high-k dielectric material. | 01-17-2013 |
20130175587 | SELF-ALIGNED CONTACT FOR REPLACEMENT GATE DEVICES - A conductive top surface of a replacement gate stack is recessed relative to a top surface of a planarization dielectric layer by at least one etch. A dielectric capping layer is deposited over the planarization dielectric layer and the top surface of the replacement gate stack so that the top surface of a portion of the dielectric capping layer over the replacement gate stack is vertically recessed relative to another portion of the dielectric layer above the planarization dielectric layer. The vertical offset of the dielectric capping layer can be employed in conjunction with selective via etch processes to form a self-aligned contact structure. | 07-11-2013 |
20130178053 | SELF-ALIGNED CONTACT EMPLOYING A DIELECTRIC METAL OXIDE SPACER - A dielectric liner is formed on sidewalls of a gate stack and a lower contact-level dielectric material layer is deposited on the dielectric liner and planarized. The dielectric liner is recessed relative to the top surface of the lower contact-level dielectric material layer and the top surface of the gate stack. A dielectric metal oxide layer is deposited and planarized to form a dielectric metal oxide spacer that surrounds an upper portion of the gate stack. The dielectric metal oxide layer has a top surface that is coplanar with a top surface of the planarized lower contact-level dielectric material layer. Optionally, the conductive material in the gate stack may be replaced. After deposition of at least one upper contact-level dielectric material layer, at least one via hole extending to a semiconductor substrate is formed employing the dielectric metal oxide spacer as a self-aligning structure. | 07-11-2013 |
20130189834 | SELF-ALIGNED CONTACTS FOR HIGH k/METAL GATE PROCESS FLOW - A semiconductor structure is provided that includes a semiconductor substrate having a plurality of gate stacks located thereon. Each gate stack includes a high k gate dielectric layer, a work function metal layer and a conductive metal. A spacer is located on sidewalls of each gate stack and a self-aligned dielectric liner is present on an upper surface of each spacer. A bottom surface of each self-aligned dielectric liner is present on an upper surface of a semiconductor metal alloy. A contact metal is located between neighboring gate stacks and is separated from each gate stack by the self-aligned dielectric liner. The structure also includes another contact metal having a portion that is located on and in direct contact with an upper surface of the contact metal and another portion that is located on and in direct contact with the conductive metal of one of the gate stacks. | 07-25-2013 |
20130313647 | FORMING FACET-LESS EPITAXY WITH A CUT MASK - A method of forming a semiconductor structure on a substrate is provided. The method may include preparing a continuous active layer on a region of the substrate and depositing a first raised epitaxial layer on a first region of the continuous active layer. A second raised epitaxial layer is also deposited on a second region of the continuous active layer such that the first raised epitaxial layer is in close proximity to the second raised epitaxial layer. A mask may be used to etch a trench structure into the continuous active layer at both the first and the second raised epitaxial layer, whereby the etched trench structure is filled with isolation material for electrically isolating the first raised epitaxial layer from the second raised epitaxial layer. | 11-28-2013 |
20140004677 | High-k Seal for Protection of Replacement Gates | 01-02-2014 |
20140027820 | FORMING FACET-LESS EPITAXY WITH SELF-ALIGNED ISOLATION - A method of forming a semiconductor structure may include preparing a continuous active layer in a region of the substrate and forming a plurality of adjacent gates on the continuous active layer. A first raised epitaxial layer may be deposited on a recessed region of the continuous active layer between a first and a second one of the plurality of gates, whereby the first and second gates are adjacent. A second raised epitaxial layer may be deposited on another recessed region of the continuous active layer between the second and a third one of the plurality of gates, whereby the second and third gates are adjacent. Using a cut mask, a trench structure is etched into the second gate structure and a region underneath the second gate in the continuous active layer. The trench is filled with isolation material for electrically isolating the first and second raised epitaxial layers. | 01-30-2014 |
20140103404 | REPLACEMENT GATE WITH AN INNER DIELECTRIC SPACER - After formation of source and drain regions and a planarization dielectric layer, a disposable gate structure is removed to form a gate cavity. A gate dielectric and a lower gate electrode are formed within the gate cavity. The lower gate electrode is vertically recessed relative to the planarization dielectric layer to form a recessed region. An inner dielectric spacer is formed within the recessed region by depositing a conformal dielectric layer and removing horizontal portions thereof by an anisotropic etch. An upper gate electrode is formed by depositing another conductive material within a remaining portion of the recessed region. A contact level dielectric layer is formed and contact structures are formed to the source and drain regions. The inner dielectric spacer prevents an electrical short between the gate electrode and a contact structure that partially overlies the gate electrode by overlay variations during lithographic processes. | 04-17-2014 |