Patent application number | Description | Published |
20110124193 | CUSTOMIZED PATTERNING MODULATION AND OPTIMIZATION - The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes providing an IC design layout of a circuit; applying an electrical patterning (ePatterning) modification to the IC design layout according to an electrical parameter of the circuit and an optical parameter of IC design layout; and thereafter fabricating a mask according to the IC design layout. | 05-26-2011 |
20110161907 | Practical Approach to Layout Migration - The present disclosure provides an integrated circuit design method in many different embodiments. An exemplary IC design method comprises providing an IC design layout of a circuit in a first technology node; migrating the IC design layout of the circuit to a second technology node; applying an electrical patterning (ePatterning) modification to the migrated IC design layout according to an electrical parameter of the circuit; and thereafter fabricating a mask according to the migrated IC design layout of the circuit in the second technology node. | 06-30-2011 |
20110204470 | METHOD, SYSTEM, AND APPARATUS FOR ADJUSTING LOCAL AND GLOBAL PATTERN DENSITY OF AN INTEGRATED CIRCUIT DESIGN - An integrated circuit (IC) design method providing a circuit design layout having a plurality of functional blocks disposed a distance away from each other; identifying a local pattern density to an approximate dummy region, on the circuit design layout, within a predefined distance to one of the functional blocks; performing a local dummy insertion to the approximate dummy region according to the local pattern density; repeating the identifying and performing to at least some other of the functional blocks; and implementing a global dummy insertion to a non-local dummy region according to a global pattern density. | 08-25-2011 |
20110214101 | METHOD OF THERMAL DENSITY OPTIMIZATION FOR DEVICE AND PROCESS ENHANCEMENT - The present disclosure provides an integrated circuit method. The method includes providing an integrated circuit (IC) design layout; simulating thermal effect to the IC design layout; simulating electrical performance to the IC design layout based on the simulating thermal effect; and performing thermal dummy insertion to the IC design layout based on the simulating electrical performance. | 09-01-2011 |
20110217630 | INTENSITY SELECTIVE EXPOSURE PHOTOMASK - An intensity selective exposure photomask, also describes as a gradated photomask, is provided. The photomask includes a first region including a first array of sub-resolution features. The first region blocks a first percentage of the incident radiation. The photomask also includes a second region including a second array of sub-resolution features. The second region blocks a second percentage of the incident radiation different that the first percentage. Each of the features of the first and second array includes an opening disposed in an area of attenuating material. | 09-08-2011 |
20120040278 | INTENSITY SELECTIVE EXPOSURE PHOTOMASK - An intensity selective exposure photomask, also describes as a gradated photomask, is provided. The photomask includes a first region including a first array of sub-resolution features. The first region blocks a first percentage of the incident radiation. The photomask also includes a second region including a second array of sub-resolution features. The second region blocks a second percentage of the incident radiation different that the first percentage. | 02-16-2012 |
20120144361 | PARAMETERIZED DUMMY CELL INSERTION FOR PROCESS ENHANCEMENT - The present disclosure relates to parameterized dummy cell insertion for process enhancement and methods for fabricating the same. In accordance with one or more embodiments, methods include providing an integrated circuit (IC) design layout with defined pixel-units, simulating thermal effect to the IC design layout including each pixel-unit, generating a thermal effect map of the IC design layout including each pixel-unit, determining a target absorption value for the IC design layout, and performing thermal dummy cell insertion to each pixel-unit of the IC design layout based on the determined target absorption value. | 06-07-2012 |
20130061196 | TARGET-BASED DUMMY INSERTION FOR SEMICONDUCTOR DEVICES - The present disclosure provides integrated circuit methods for target-based dummy insertion. A method includes providing an integrated circuit (IC) design layout, and providing a thermal model for simulating thermal effect on the IC design layout, the thermal model including optical simulation and silicon calibration. The method further includes providing a convolution of the thermal model and the IC design layout to generate a thermal image profile of the IC design layout, defining a thermal target for optimizing thermal uniformity across the thermal image profile, comparing the thermal target and the thermal image profile to determine a difference data, and performing thermal dummy insertion to the IC design layout based on the difference data to provide a target-based IC design layout. | 03-07-2013 |
20130267047 | Topography-Aware Lithography Pattern Check - The present disclosure provides a method. The method includes obtaining an integrated circuit (IC) layout. The method includes providing a polishing process simulation model. The method includes performing a lithography pattern check (LPC) process to the IC layout. The LPC process is performed at least in part using the polishing process simulation model. The method includes detecting, in response to the LPC process, possible problem areas on the IC layout. The method includes modifying the polishing process simulation model. The method includes repeating the performing the LPC process and the detecting the possible problem areas using the modified polishing process simulation model. | 10-10-2013 |
20140170537 | METHOD OF DEFINING AN INTENSITY SELECTIVE EXPOSURE PHOTOMASK - An embodiment of a feed-forward method of determining a photomask pattern is provided. The method includes providing design data associated with an integrated circuit device. A thickness of a coating layer to be used in fabricating the integrated circuit device is predicted based on the design data. This prediction is used to generate a gradating pattern. A photomask is formed having the gradating pattern. | 06-19-2014 |
20150100927 | Chip Level Critical Point Analysis with Manufacturer Specific Data - A method and computer program are provided for analyzing a set of layers within an integrated circuit design to determine a set of critical points for each layer within the set of layers. The critical points are based at least in part on manufacturer specific process parameters. The method includes assigning a critical point value to each of the critical points within each set of critical points, analyzing a path through the integrated circuit design across multiple integrated circuit design layers, and determining a sum of critical point values of each critical point along the path. | 04-09-2015 |
Patent application number | Description | Published |
20090011910 | Auxiliary structure for fitness equipment efficacy - An auxiliary structure to improve efficacy of a fitness equipment includes a pair of swing bars pivoted to a pair of traction bars wherein in turn pivoted to a crank; the crank drives a sprocket and a resistance control wheel for both swing bars to drive both traction bars to travel up, down, back and forth; each pedal is disposed with a roller to travel in a slide attached to the traction bar and is pivoted to a pull-and-push connection bar, which in turn is pivoted to a transmission connection bar; each transmission connection bar is pivoted to a support; each mid section of the transmission connection bar is pivoted to an active connection bar, which in turn is pivoted to the swing bar; and each pedal is dragged by the push-and-pull connection bar driven by the transmission connection bar when both swing bars alternatively swing to drive the transmission connecting bar to increase longitudinal travel ranges of both pedals for providing adequate exercise amount for waist and legs of a user to improve exercise efficacy. | 01-08-2009 |
20110071005 | Stepping and Waist Twirling Exercise Machine - A stepping and waist twirling exercise machine includes left and right stepping rods having left and right through holes and left and right stepping platforms having left and right shafts. The shafts are inserted into bearings provided in the through holes. Left and right coil rollers are provided on the shafts. The coil rollers are provided with left and right rope units each having left and right ropes. The ropes have first ends and second ends. The first ends of the ropes are secured to two sides of the coil rollers, respectively. The second ends of the ropes are secured to a frame and a machine base, respectively. When the left and right stepping platforms are stepped downward in turn, the left and right rope units will bring the left and right coil rollers to turn left or right synchronously, providing active or passive stepping and waist twirling exercise. | 03-24-2011 |
20110071006 | Transmission Structure of a Waist Twirling Exercise Machine for Body-Building and a Method Thereof - A transmission structure of a waist twirling exercise machine for body-building and a method thereof includes left and right stepping rods which are obliquely or horizontally connected to a machine base, left and right stepping platforms having left and right shafts inserting through lubricating members provided in through holes of the left and right stepping rods, left and right transmission members having first ends connected to the left and right shafts and second ends provided with eccentric blocks, left and right connecting rods having first ends connected to the eccentric blocks of the left and right transmission members and second ends pivotally connected to either of the machine base and pneumatic cylinders. When the left and right stepping platforms are treaded in turn, the left and right connecting rods subject to their lengths will drive the left and right stepping platforms to turn left and right in turn synchronously, enhancing a waist twirling effect. | 03-24-2011 |
20110294627 | Oval Transmission Structure - An oval transmission structure utilizes lower ends of swaying moving shafts at two sides thereof to pivot to front ends of push-pull shafts, whose front portions slope to a determined angle. Rear portions of the push-pull shafts offer treadle frames for treadles to dispose with feet. Rear portions of the push-pull shafts further offer a track frame. An assistant device provides a sliding block with a fixing bolt superimposed at a side of the lower portion of the swaying moving shaft. An attached shaft pivoted to a side of the sliding block connects to an axle bolt of a transmission shaft, whose front end axially connects to a crank, whose rear end serially connects to a track wheel and whose middle determined position disposes a sliding wheel thereunder. The reciprocation brought about by the feet, the two cranks axially trigger the front ends of the two transmission shaft for achieving a relative oval action. The axle bolt motivates the attached shaft for driving the sliding block to move the lower portions of the two swaying moving shafts to achieve a relative displacement. Concurrently, the sliding wheel reciprocating flat on the track frame permits upper portions of the swaying moving shafts to sway oppositely. The two treadle frames accordingly slide on the track wheels. A V-shaped leverage of the transmission shaft could attain a favorable transmission effect in time of users operating the back-and-forth reciprocation. | 12-01-2011 |
20120035022 | EXERCISE MACHINE - An exercise machine comprises an oval-shaped structure, two driving arms, two swing handle and two slidable bars. The fly wheel of the oval-shaped mechanism simultaneously drives the driving arms and the swing handle, and the slidable bars are pivoted onto the assembling portion of the swing handle and rest on the shaft of the fly wheel such that the movements of the slidable bars are not limited by the driving arms and longer the travel stroke of the fly wheel. | 02-09-2012 |
20120322623 | EXERCISE MACHINE - An exercise machine comprises an oval-shaped structure, two driving arms, two swing handles and two slidable bars. With the above-mentioned embodiments, following benefits can be obtained, the fly wheel of the oval-shaped structure utilizes the assembling section to be connected an adjusting member, such that the movement strokes can be adjusted. | 12-20-2012 |
Patent application number | Description | Published |
20130292832 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package includes: a first insulating layer; a plurality of first conductive elements disposed in the first insulating layer; a first circuit layer formed on the first insulating layer; a semiconductor chip disposed on the first insulating layer; and an encapsulant formed on the first insulating layer and encapsulating the semiconductor chip. The first conductive elements that are bonding wires have a small diameter and thus occupy desired limited space on the first insulating layer. Therefore, more space is available for the first circuit layer. | 11-07-2013 |
20130307152 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A fabrication method of a semiconductor package is provided, which includes the steps of: forming a packaging substrate on a first carrier; bonding a second carrier to the packaging substrate; removing the first carrier; disposing a chip on the packaging substrate; forming an encapsulant on the packaging substrate for encapsulating the chip; and removing the second carrier. The first and second carriers provide the thin-type packaging substrate with sufficient rigidity for undergoing the fabrication processes without cracking or warpage, thereby meeting the miniaturization requirement and improving the product yield. | 11-21-2013 |
20130334694 | PACKAGING SUBSTRATE, SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A packaging substrate is provided, including: a metal board having a first surface and a second surface opposite to the first surface, wherein the first surface has a plurality of first openings for defining a first core circuit layer therebetween, the second surface has a plurality of second openings for defining a second core circuit layer therebetween, each of the first and second openings has a wide outer portion and a narrow inner portion, and the inner portion of each of the second openings is in communication with the inner portion of a corresponding one of the first openings; a first encapsulant formed in the first openings; a second encapsulant formed in the second openings; and a surface circuit layer formed on the first encapsulant and the first core circuit layer. The present invention effectively reduces the fabrication cost and increases the product reliability. | 12-19-2013 |
20140091462 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package is provided, which includes: a dielectric layer made of a material used for fabricating built-up layer structures; a conductive trace layer formed on the dielectric layer; a semiconductor chip is mounted on and electrically connected to the conductive trace layer; and an encapsulant formed over the dielectric layer to encapsulate the semiconductor chip and the conductive trace layer. Since a strong bonding is formed between the dielectric layer and the conductive trace layer, the present invention can prevent delamination between the dielectric layer and the conductive trace layer from occurrence, thereby improving reliability and facilitating the package miniaturization by current fabrication methods. | 04-03-2014 |
20140308780 | FABRICATION METHOD OF SEMICONDUCTOR PACKAGE - A fabrication method of a semiconductor package is provided, which includes the steps of: forming a packaging substrate on a first carrier; bonding a second carrier to the packaging substrate; removing the first carrier; disposing a chip on the packaging substrate; forming an encapsulant on the packaging substrate for encapsulating the chip; and removing the second carrier. The first and second carriers provide the thin-type packaging substrate with sufficient rigidity for undergoing the fabrication processes without cracking or warpage, thereby meeting the miniaturization requirement and improving the product yield. | 10-16-2014 |
20140315353 | FABRICATION METHOD OF PACKAGING SUBSTRATE, AND FABRICATION METHOD OF SEMICONDUCTOR PACKAGE - A fabrication method of a packaging substrate includes: providing a metal board having a first surface and a second surface opposite to the first surface, wherein the first surface has a plurality of first openings for defining a first core circuit layer therebetween, the second surface has a plurality of second openings for defining a second core circuit layer therebetween, each of the first and second openings has a wide outer portion and a narrow inner portion, and the inner portion of each of the second openings is in communication with the inner portion of a corresponding one of the first openings; a first encapsulant in the first openings; a second encapsulant in the second openings; and forming a surface circuit layer on the first encapsulant and the first core circuit layer. | 10-23-2014 |
20150091150 | PACKAGE ON PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF - A method for fabricating a POP structure is disclosed. First, a first package is provided, which has: a dielectric layer; a stacked circuit layer embedded in the dielectric layer and exposed from upper and lower surfaces of the dielectric layer; a plurality of conductive posts and a semiconductor chip disposed on the upper surface of the dielectric layer and electrically connected to the stacked circuit layer; and an encapsulant formed on upper surface of the dielectric layer for encapsulating the semiconductor chip and the conductive posts and having a plurality of openings for exposing top ends of the conductive posts. Then, a second package is disposed on the encapsulant and electrically connected to the conductive posts. The formation of the conductive posts facilitates to reduce the depth of the openings of the encapsulant, thereby reducing the fabrication time and increasing the production efficiency and yield. | 04-02-2015 |
20150144384 | PACKAGING SUBSTRATE AND FABRICATION METHOD THEREOF - A packaging substrate is disclosed, which includes: a dielectric layer; a circuit layer embedded in and exposed from a surface of the dielectric layer, wherein the circuit layer has a plurality of conductive pads; and a plurality of conductive bumps formed on the conductive pads and protruding above the surface of the dielectric layer. As such, when an electronic element is disposed on the conductive pads through a plurality of conductive elements, the conductive elements can come into contact with both top and side surfaces of the conductive bumps so as to increase the contact area between the conductive elements and the conductive pads, thereby strengthening the bonding between the conductive elements and the conductive pads and preventing delamination of the conductive elements from the conductive pads. | 05-28-2015 |
20150187603 | FABRICATION METHOD OF PACKAGING SUBSTRATE - A fabrication method of a packaging substrate includes: providing a metal board having a first surface and a second surface opposite to the first surface, wherein the first surface has a plurality of first openings for defining a first core circuit layer therebetween, the second surface has a plurality of second openings for defining a second core circuit layer therebetween, each of the first and second openings has a wide outer portion and a narrow inner portion, and the inner portion of each of the second openings is in communication with the inner portion of a corresponding one of the first openings; forming a first encapsulant in the first openings; forming a second encapsulant in the second openings; and forming a surface circuit layer on the first encapsulant and the first core circuit layer. | 07-02-2015 |