Patent application number | Description | Published |
20090107954 | METHOD FOR CONTROLLING ADI-AEI CD DIFFERENCE RATIO OF OPENINGS HAVING DIFFERENT SIZES - A method for controlling ADI-AEI CD difference ratios of openings having different sizes is provided. First, a first etching step using a patterned photoresist layer as a mask is performed to form a patterned Si-containing material layer and a polymer layer on sidewalls thereof. Next, a second etching step is performed with the patterned photoresist layer, the patterned Si-containing material layer and the polymer layer as masks to at least remove an exposed portion of a etching resistive layer to form a patterned etching resistive layer. A portion of a target material layer is removed by using the patterned etching resistive layer as an etching mask to form a first and a second openings in the target material layer. The method is characterized by controlling etching parameters of the first and second etching steps to obtain predetermined ADI-AEI CD difference ratios. | 04-30-2009 |
20090145877 | METHOD FOR CONTROLLING ADI-AEI CD DIFFERENCE RATIO OF OPENINGS HAVING DIFFERENT SIZES - A method for controlling an ADI-AEI CD difference ratio of openings having different sizes is described. The openings are formed through a silicon-containing material layer, an etching resistive layer and a target material layer in turn. Before the opening etching steps, at least one of the opening patterns in the photoresist mask is altered in size through photoresist trimming or deposition of a substantially conformal polymer layer. A first etching step forming thicker polymer on the sidewall of the wider opening pattern is performed to form a patterned Si-containing material layer. A second etching step is performed to remove exposed portions of the etching resistive layer and the target material layer. At least one parameter among the parameters of the photoresist trimming or polymer layer deposition step and the etching parameters of the first etching step is controlled to obtain a predetermined ADI-AEI CD difference ratio. | 06-11-2009 |
20100317195 | METHOD FOR FABRICATING AN APERTURE - A method for fabricating an aperture is disclosed. The method includes the steps of: depositing a dielectric layer and a hard mask on surface of a semiconductor substrate; patterning the hard mask by forming an aperture in the hard mask; utilizing a gas containing C | 12-16-2010 |
20110006437 | OPENING STRUCTURE - An opening structure includes a semiconductor substrate, at least one dielectric layer disposed on the semiconductor substrate, wherein the dielectric layer has a plurality of openings exposing the semiconductor substrate, and each of the openings has a sidewall, a dielectric thin film covering at least a portion of the sidewall of each of the openings, and a metal layer filled in the openings. | 01-13-2011 |
20110174774 | METHOD OF DESCUMMING PATTERNED PHOTORESIST - A method of descumming a patterned photoresist is provided. First a material layer to be etched is provided. The material layer is covered by a patterned photoresist. Then a descum process is preformed to descum the edge of the patterned photoresist by nitrogen. Finally, the descummed patterned photoresist is used as a mask for etching the material layer. | 07-21-2011 |
20110223768 | Method for Forming Contact Opening - A method for forming contact openings is provided. First, a semiconductor device is formed on a substrate. Next, an etching stop layer, a first dielectric layer and a patterned photoresist layer are sequentially formed on the substrate. Next a portion of the first dielectric layer and a portion of the etching stop layer are removed to form an opening, wherein the portion of the first dielectric layer and the portion of the etching stop layer are not covered by the patterned photoresist layer. Next, the patterned photoresist layer is removed. Next, an over etching process is performed to remove the etching stop layer at a bottom of the opening and expose the semiconductor device in a nitrogen-free environment. The reactant gas of the over etching process includes fluorine-containing hydrocarbons, hydrogen gas and argon gas. | 09-15-2011 |
20120001338 | OPENING STRUCTURE - An opening structure is disclosed. The opening structure includes: a semiconductor substrate; at least one dielectric layer disposed on the semiconductor substrate, wherein the dielectric layer has a plurality of openings exposing the semiconductor substrate, and each of the openings has a sidewall; a dielectric thin film covering at least a portion of the sidewall of each of the openings; an etch stop layer disposed between the semiconductor substrate and the dielectric layer and extending partially into the openings to isolate the dielectric thin film from the semiconductor substrate; and a metal layer filled in the openings. | 01-05-2012 |
20120270403 | METHOD OF FABRICATING OPENINGS - A method of fabricating openings is disclosed. First, a semiconductor substrate having a salicide region thereon is provided. An etch stop layer and at least a dielectric layer are disposed on the semiconductor substrate from bottom to top. Second, the dielectric layer and the etching stop layer are patterned to form a plurality of openings in the dielectric layer and in the etching stop layer so that the openings expose the salicide region. Then, a dielectric thin film covering the dielectric layer, sidewalls of the openings and the salicide region is formed. Later, the dielectric thin film disposed on the dielectric layer and on the salicide region is removed. | 10-25-2012 |
20130093062 | SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF - A semiconductor structure includes a substrate, a recess and a material. The recess is located in the substrate, wherein the recess has an upper part and a lower part. The minimum width of the upper part is larger than the maximum width of the lower part. The material is located in the recess. | 04-18-2013 |
20140035066 | Non-Planar FET and Manufacturing Method Thereof - The present invention provides a non-planar FET which includes a substrate, a fin structure, a sub spacer, a gate, a dielectric layer and a source/drain region. The fin structure is disposed on the substrate. The sub spacer is disposed only on a middle sidewall of the fin structure. The gate is disposed on the fin structure. The dielectric layer is disposed between the fin structure and the gate. The source/drain region is disposed in the fin structure. The present invention further provides a method of forming the same. | 02-06-2014 |
20140038417 | SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF - A semiconductor structure includes a substrate, a recess and a material. The recess is located in the substrate, wherein the recess has an upper part and a lower part. The minimum width of the upper part is larger than the maximum width of the lower part. The material is located in the recess. | 02-06-2014 |