Patent application number | Description | Published |
20090322795 | METHOD AND APPARATUS FOR REDUCING POWER CONSUMPTION FOR DISPLAYS - A system, apparatus and method to reduce power consumption for displays is described. The method may include receiving image data comprising a plurality of color components, generating a histogram for each of the plurality of color components, and adjusting each of a plurality of light sources based on the histograms. The plurality of light sources may correspond to the plurality of color components. Other embodiments are described and claimed. | 12-31-2009 |
20090327777 | POWER EFFICIENT HIGH FREQUENCY DISPLAY WITH MOTION BLUR MITIGATION - Some embodiments describe techniques that relate to power efficient, high frequency displays with motion blur mitigation. In one embodiment, the refresh rate of a display device may be dynamically modified, e.g., to reduce power consumption and/or reduce motion blur. Other embodiments are also described. | 12-31-2009 |
20100253611 | Method and apparatus for adaptive black frame insertion - In some embodiments, a display device may include a flat panel display a controller coupled to the flat panel display. The controller may be configured to determine an operating mode for the flat panel display among a plurality of operating modes including at least a first operating mode and a second operating mode. In the first operating mode, the controller may set the flat panel display to utilize a first frame rate and a first inversion mode to save power. In the second operating mode, the controller may set the flat panel display to utilize a second frame rate, a second inversion mode, and black frame insertion to improve image quality. The second frame rate may be faster than the first frame rate. The second inversion mode and black frame insertion may be mutually configured to maintain a DC balanced operation of the flat panel display. Other embodiments are disclosed and claimed. | 10-07-2010 |
20110157212 | Techniques for adapting a color gamut - Techniques are described that can be used to provide color space conversion for images and video to a display color gamut space. Some techniques provide for accessing an sRGB gamut color table, determining a color conversion matrix based on the sRGB gamut color table and chromaticity values of RGBW primary and gamma stored in the display or associated with the display, applying color space conversion to the pixels for pixels using the color conversion matrix, and applying linear correction of pixels by applying a normalization factor to the color conversion matrix. In addition, some techniques provide analysis of content gamut with respect to display gamut in HSV space, adjustment in HSV space, and conversion back to RGB space before applying color space conversion. | 06-30-2011 |
20110181611 | USER INTERFACE AND CONTROL OF SEGMENTED BACKLIGHT DISPLAY - In some embodiments a user interface is adapted to monitor user inputs and one or more controllers are adapted to modify backlight segment brightness and/or image pixel values of a segmented backlight display in response to the monitored user inputs. Other embodiments are described and claimed. | 07-28-2011 |
20110291171 | VARACTOR - A variable capacitance device including a plurality of FETs, the sources and drains of each FET being coupled to a first terminal, the gates of each FET being coupled to a second terminal, the capacitance of said device between said first and second terminals varying as a function of the voltage across said terminals, the device further including a biasing providing a respective backgate bias voltage to each the FETs setting a respective gate threshold voltage thereof. The aggregate V-C characteristic can be tuned as desired, either at design time or dynamically. The greater the number of FETs forming the varactor, the greater the number of possible Vt values that can be individually set, so that arbitrary V-C characteristics can be more closely approximated. | 12-01-2011 |
20120064694 | FORMING IMPLANTED PLATES FOR HIGH ASPECT RATIO TRENCHES USING STAGED SACRIFICIAL LAYER REMOVAL - A method of forming a deep trench structure for a semiconductor device includes forming a mask layer over a semiconductor substrate. An opening in the mask layer is formed by patterning the mask layer, and a deep trench is formed in the semiconductor substrate using the patterned opening in the mask layer. A sacrificial fill material is formed over the mask layer and into the deep trench. A first portion of the sacrificial fill material is recessed from the deep trench and a first dopant implant forms a first doped region in the semiconductor substrate. A second portion of the sacrificial fill material is recessed from the deep trench and a second dopant implant forms a second doped region in the semiconductor substrate, wherein the second doped region is formed underneath the first doped region such that the second doped region and the first doped region are contiguous with each other. | 03-15-2012 |
20120086077 | FET STRUCTURES WITH TRENCH IMPLANTATION TO IMPROVE BACK CHANNEL LEAKAGE AND BODY RESISTANCE - An FET structure on a semiconductor substrate which includes forming recesses for a source and a drain of the gate structure on a semiconductor substrate, halo implanting regions through the bottom of the source and drain recesses, the halo implanted regions being underneath the gate stack, implanting junction butting at the bottom of the source and drain recesses, and filling the source and drain recesses with a doped epitaxial material. In exemplary embodiments, the semiconductor substrate is a semiconductor on insulator substrate including a semiconductor layer on a buried oxide layer. In exemplary embodiments, the junction butting and halo implanted regions are in contact with the buried oxide layer. In other exemplary embodiments, there is no junction butting. In exemplary embodiments, halo implants implanted to a lower part of the FET body underneath the gate structure provide higher doping level in lower part of the FET body to reduce body resistance, without interfering with FET threshold voltage. | 04-12-2012 |
20120122303 | SEMICONDUCTOR STRUCTURE HAVING WIDE AND NARROW DEEP TRENCHES WITH DIFFERENT MATERIALS - Disclosed is a method of forming a semiconductor device structure in a semiconductor layer. The method includes forming a first trench of a first width and a second trench of a second width in the semiconductor layer; depositing a layer of first material which conforms to a wall of the first trench but does not fill it and which fills the second trench; removing the first material from the first trench, the first material remaining in the second trench; depositing a second material into and filling the first trench and over a top of the first material in the second trench; and uniformly removing the second material from the top of the first material in the second trench, wherein the first trench is filled with the second material and the second trench is filled with the first material and wherein the first material is different from the second material. | 05-17-2012 |
20120187490 | FET STRUCTURES WITH TRENCH IMPLANTATION TO IMPROVE BACK CHANNEL LEAKAGE AND BODY RESISTANCE - A field effect transistor (FET) structure on a semiconductor substrate which includes a gate structure having a spacer on a semiconductor substrate; an extension implant underneath the gate structure; a recessed source and a recessed drain filled with a doped epitaxial material; halo implanted regions adjacent a bottom of the recessed source and drain and being underneath the gate stack. In an exemplary embodiment, there is implanted junction butting underneath the bottom of each of the recessed source and drain, the junction butting being separate and distinct from the halo implanted regions. In another exemplary embodiment, the doped epitaxial material is graded from a lower dopant concentration at a side of the recessed source and drain to a higher dopant concentration at a center of the recessed source and drain. In a further exemplary embodiment, the semiconductor substrate is a semiconductor on insulator substrate. | 07-26-2012 |
20120199945 | METHOD OF FORMING DEEP TRENCH CAPACITOR - Aspects of the invention provide for methods of forming a deep trench capacitor structure. In one embodiment, aspects of the invention include a method of forming a deep trench capacitor structure, including: forming a deep trench within a semiconductor substrate; depositing a first liner within the deep trench; filling a lower portion of the deep trench with a filler material; depositing a second liner within an upper portion of the deep trench; removing the filler material, such that the lower portion of the deep trench includes only the first liner and the upper portion of the deep trench includes the first liner and the second liner; forming a high doped region around the lower portion of the deep trench; and removing the first liner within the lower portion of the deep trench and the second liner within the upper portion of the deep trench. | 08-09-2012 |
20130032859 | EPITAXIAL EXTENSION CMOS TRANSISTOR - A pair of horizontal-step-including trenches are formed in a semiconductor layer by forming a pair of first trenches having a first depth around a gate structure on the semiconductor layer, forming a disposable spacer around the gate structure to cover proximal portions of the first trenches, and by forming a pair of second trenches to a second depth greater than the first depth. The disposable spacer is removed, and selective epitaxy is performed to form an integrated epitaxial source and source extension region and an integrated epitaxial drain and drain extension region. A replacement gate structure can be formed after deposition and planarization of a planarization dielectric layer and subsequent removal of the gate structure and laterally expand the gate cavity over expitaxial source and drain extension regions. Alternately, a contact-level dielectric layer can be deposited directly on the integrated epitaxial regions and contact via structures can be formed therein. | 02-07-2013 |
20130113694 | METHOD AND APPARATUS FOR ADAPTIVE BLACK FRAME INSERTION - In some embodiments, a display device may include a flat panel display a controller coupled to the flat panel display. The controller may be configured to determine an operating mode for the flat panel display among a plurality of operating modes including at least a first operating mode and a second operating mode. In the first operating mode, the controller may set the flat panel display to utilize a first frame rate and a first inversion mode to save power. In the second operating mode, the controller may set the flat panel display to utilize a second frame rate, a second inversion mode, and black frame insertion to improve image quality. The second frame rate may be faster than the first frame rate. The second inversion mode and black frame insertion may be mutually configured to maintain a DC balanced operation of the flat panel display. Other embodiments are disclosed and claimed. | 05-09-2013 |
20130168822 | SELF ALIGNED STRUCTURES AND DESIGN STRUCTURE THEREOF - Vertical bipolar junction structures, methods of manufacture and design structures. The method includes forming one or more sacrificial structures for a bipolar junction transistor (BJT) in a first region of a chip. The method includes forming a mask over the one or more sacrificial structures. The method further includes etching an opening in the mask, aligned with the one or more sacrificial structures. The method includes forming a trench through the opening and extending into diffusion regions below the one or more sacrificial structures. The method includes forming a base region of the BJT by depositing an epitaxial material in the trench, in contact with the diffusion regions. The method includes forming an emitter contact by depositing a second epitaxial material on the base region within the trench. The epitaxial material for the emitter region is of an opposite dopant type than the epitaxial material of the base region. | 07-04-2013 |
20130171794 | EPITAXIAL EXTENSION CMOS TRANSISTOR - A pair of horizontal-step-including trenches are formed in a semiconductor layer by forming a pair of first trenches having a first depth around a gate structure on the semiconductor layer, forming a disposable spacer around the gate structure to cover proximal portions of the first trenches, and by forming a pair of second trenches to a second depth greater than the first depth. The disposable spacer is removed, and selective epitaxy is performed to form an integrated epitaxial source and source extension region and an integrated epitaxial drain and drain extension region. A replacement gate structure can be formed after deposition and planarization of a planarization dielectric layer and subsequent removal of the gate structure and laterally expand the gate cavity over expitaxial source and drain extension regions. Alternately, a contact-level dielectric layer can be deposited directly on the integrated epitaxial regions and contact via structures can be formed therein. | 07-04-2013 |
20130189826 | Reduced Corner Leakage in SOI Structure and Method - A structural alternative to retro doping to reduce transistor leakage is provided by providing a liner in a trench, undercutting a conduction channel region in an active semiconductor layer, etching a side, corner and/or bottom of the conduction channel where the undercut exposes semiconductor material in the active layer and replacing the removed portion of the conduction channel with insulator. This shaping of the conduction channel increases the distance to adjacent circuit elements which, if charged, could otherwise induce a voltage and cause a change in back-channel threshold in regions of the conduction channel and narrows and reduces cross-sectional area of the channel where the conduction in the channel is not well-controlled; both of which effects significantly reduce leakage of the transistor. | 07-25-2013 |
20130248974 | COMPACT THREE DIMENSIONAL VERTICAL NAND AND METHOD OF MAKING THEREOF - A NAND device has at least a 3×3 array of vertical NAND strings in which the control gate electrodes are continuous in the array and do not have an air gap or a dielectric filled trench in the array. The NAND device is formed by first forming a lower select gate level having separated lower select gates, then forming plural memory device levels containing a plurality of NAND string portions, and then forming an upper select gate level over the memory device levels having separated upper select gates. | 09-26-2013 |
20130278616 | RESOLUTION LOSS MITIGATION FOR 3D DISPLAYS - Systems, devices and methods are described including determining a display type and a display mode, preparing stereoscopic image content in response to the display mode, where preparing the stereoscopic image content includes storing a full resolution left image and a full resolution right image in memory, and determining a display refresh rate in response to at least a content frame rate of the stereoscopic image content. The stereoscopic image content may then be processed for display according to the display type, the display refresh rate, and a power policy. | 10-24-2013 |
20130328950 | METHOD AND APPARATUS FOR REDUCING POWER CONSUMPTION FOR DISPLAYS - A system, apparatus and method to reduce power consumption for displays is described. The method may include receiving image data comprising a plurality of color components, generating a histogram for each of the plurality of color components, and adjusting each of a plurality of light sources based on the histograms. The plurality of light sources may correspond to the plurality of color components. Other embodiments are described and claimed. | 12-12-2013 |
20140035064 | SEMICONDUCTOR STRUCTURES AND METHODS OF MANUFACTURE - Semiconductor structures and methods of manufacture are disclosed herein. Specifically, disclosed herein are methods of manufacturing a high-voltage metal-oxide-semiconductor field-effect transistor and respective structures. A method includes forming a field-effect transistor (FET) on a substrate in a FET region, forming a high-voltage FET (HVFET) on a dielectric stack over a over lightly-doped diffusion (LDD) drain in a HVFET region, and forming an NPN on the substrate in an NPN region. | 02-06-2014 |
20140054664 | POLYSILICON/METAL CONTACT RESISTANCE IN DEEP TRENCH - A method of forming a trench structure that includes forming a metal containing layer on at least the sidewalls of a trench, and forming an undoped semiconductor fill material within the trench. The undoped semiconductor fill material and the metal containing layer are recessed to a first depth within the trench with a first etch. The undoped semiconductor fill material is then recessed to a second depth within the trench that is greater than a first depth with a second etch. The second etch exposes at least a sidewall portion of the metal containing layer. The trench is filled with a doped semiconductor containing material fill, wherein the doped semiconductor material fill is in direct contact with the at least the sidewall portion of the metal containing layer. | 02-27-2014 |
20140062329 | DISPLAY BACKLIGHT MODULATION - An apparatus may include a backlight for illuminating a liquid crystal display and a control module for controlling the illumination of the backlight. The control module may alternate between turning the backlight on and off at a first frequency and turning the backlight on and off at a second frequency. | 03-06-2014 |
20140126291 | 3D STACKED NON-VOLATILE STORAGE PROGRAMMING TO CONDUCTIVE STATE - Programming NAND strings in a 3D stacked storage device to a conductive state is disclosed. Storage elements may be erased by raising their Vt and programmed by lowering their Vt. Programming may include applying a series of increasing voltages to selected bit lines until the selected memory cell is programmed. Unselected bit lines may be held at about ground, or close to ground. The selected word line may be grounded, or be held close to ground. Unselected word lines between the selected word line and the bit line may receive about the selected bit line voltage. Unselected word lines between the source line and the selected word line may receive about half the selected bit line voltage. Programming may be achieved without boosting channels of unselected NAND strings to inhibit them from programming. Therefore, program disturb associated with leakage of boosted channel potential may be avoided. | 05-08-2014 |
20140131782 | SEMICONDUCTOR DEVICE HAVING DIFFUSION BARRIER TO REDUCE BACK CHANNEL LEAKAGE - A semiconductor-on-insulator (SOI) substrate comprises a bulk semiconductor substrate, a buried insulator layer formed on the bulk substrate and an active semiconductor layer formed on the buried insulator layer. Impurities are implanted near the interface of the buried insulator layer and the active semiconductor layer. A diffusion barrier layer is formed between the impurities and an upper surface of the active semiconductor layer. The diffusion barrier layer prevents the impurities from diffusing therethrough. | 05-15-2014 |
20140218349 | POWER EFFICIENT HIGH FREQUENCY DISPLAY WITH MOTION BLUR MITIGATION - Some embodiments describe techniques that relate to power efficient, high frequency displays with motion blur mitigation. In one embodiment, the refresh rate of a display device may be dynamically modified, e.g., to reduce power consumption and/or reduce motion blur. Other embodiments are also described. | 08-07-2014 |
20140247288 | CONTENT ADAPTIVE POWER MAGNEMENT OF PROJECTOR SYSTEMS - Content adaptive power management technologies of projector systems are described. One method analyzes image data to be displayed by a projector system. A projector brightness of a light source of the projector system is adjusted based on the analyzed image data. The pixel values of the image data input into an imager of the projector system are adjusted based on the analyzed image data. | 09-04-2014 |
20140353738 | FLOATING GATE ULTRAHIGH DENSITY VERTICAL NAND FLASH MEMORY AND METHOD OF MAKING THEREOF - A method of making a monolithic three dimensional NAND string including providing a stack of alternating first material layers and second material layers over a substrate. The first material layers comprise an insulating material and the second material layers comprise sacrificial layers. The method also includes forming a back side opening in the stack, selectively removing the second material layers through the back side opening to form back side recesses between adjacent first material layers and forming a blocking dielectric inside the back side recesses and the back side opening. The blocking dielectric has a clam shaped regions inside the back side recesses. The method also includes forming a plurality of copper control gate electrodes in the respective clam shell shaped regions of the blocking dielectric in the back side recesses. | 12-04-2014 |
20150037950 | COMPACT THREE DIMENSIONAL VERTICAL NAND AND METHOD OF MAKING THEREOF - A NAND device has at least a 3×3 array of vertical NAND strings in which the control gate electrodes are continuous in the array and do not have an air gap or a dielectric filled trench in the array. The NAND device is formed by first forming a lower select gate level having separated lower select gates, then forming plural memory device levels containing a plurality of NAND string portions, and then forming an upper select gate level over the memory device levels having separated upper select gates. | 02-05-2015 |
20150041895 | SEMICONDUCTOR STRUCTURES AND METHODS OF MANUFACTURE - Semiconductor structures and methods of manufacture are disclosed herein. Specifically, disclosed herein are methods of manufacturing a high-voltage metal-oxide-semiconductor field-effect transistor and respective structures. A method includes forming a field-effect transistor (FET) on a substrate in a FET region, forming a high-voltage FET (HVFET) on a dielectric stack over a over lightly-doped diffusion (LDD) drain in a HVFET region, and forming an NPN on the substrate in an NPN region. | 02-12-2015 |
20150056760 | SEMICONDUCTOR DEVICE HAVING DIFFUSION BARRIER TO REDUCE BACK CHANNEL LEAKAGE - A semiconductor-on-insulator (SOI) substrate comprises a bulk semiconductor substrate, a buried insulator layer formed on the bulk substrate and an active semiconductor layer formed on the buried insulator layer. Impurities are implanted near the interface of the buried insulator layer and the active semiconductor layer. A diffusion barrier layer is formed between the impurities and an upper surface of the active semiconductor layer. The diffusion barrier layer prevents the impurities from diffusing therethrough. | 02-26-2015 |