Patent application number | Description | Published |
20120299622 | Internal Clock Gating Apparatus - An internal clock gating apparatus comprises a static logic block and a domino logic block. The static logic block is configured to receive a clock signal and a clock enable signal. The domino logic block is configured to receive the clock signal and a control signal from an output of the static logic block. The static logic block and the domino logic block are further configured such that an output of the domino logic block generates a signal similar to the clock signal in phase when the clock enable signal has a logic high state. On the other hand, the output of the domino logic block generates a logic low signal when the clock enable signal has a logic low state. Furthermore, the static logic block and the domino logic block can reduce the setup time and delay time of the internal clock gating apparatus respectively. | 11-29-2012 |
20140211574 | VOLTAGE DIVIDER CONTROL CIRCUIT - One or more techniques or systems for controlling a voltage divider are provided herein. In some embodiments, a control circuit is configured to bias a pull up unit of a voltage divider using an analog signal, thus enabling the voltage divider to be level tunable. In other words, the control circuit enables the voltage divider to output multiple voltage levels. Additionally, the control circuit is configured to bias the pull up unit based on a bias timing associated with a pull down unit of the voltage divider. For example, the pull up unit is activated after the pull down unit is activated. In this manner, the control circuit provides a timing boost, thus enabling the voltage divider to stabilize more quickly. | 07-31-2014 |
20140233330 | WRITE ASSIST CIRCUIT, MEMORY DEVICE AND METHOD - A write assist circuit includes a first switch, a second switch and a bias voltage circuit. The first switch connects a cell supply voltage node of a memory cell to a power supply voltage node in response to a write control signal having a first state, and disconnects the cell supply voltage node from the power supply voltage node in response to the write control signal having a second state. The bias voltage circuit generates, at an output thereof, an adjustable bias voltage lower than the power supply voltage. The second switch connects the cell supply voltage node to the output of the bias voltage circuit in response to the write control signal having the second state, and disconnects the cell supply voltage node from the output of the bias voltage circuit in response to the write control signal having the first state. | 08-21-2014 |
20150121030 | HIGH DENSITY MEMORY STRUCTURE - A semiconductor memory comprises a plurality of sub banks each including one or more rows of memory bit cells connected to a set of local bit lines, wherein the sub banks share a same set of global bit lines for reading/writing data from/to the memory bit cells of the sub banks. The semiconductor memory chip further comprises a plurality of switch elements for each of the sub banks, wherein each of the switch elements connects the local bit line and the global bit line of a corresponding one of the memory bit cells in the sub bank for data transmission between the local bit line and the global bit line. The semiconductor memory chip further comprises a plurality of bank selection signal lines each connected to the switch elements in a corresponding one of the sub banks, wherein the bank selection signal lines carry a plurality of bank selection signals to select one of the sub banks for data transmission between the local bit lines and the global bit lines. | 04-30-2015 |
20150131364 | NEGATIVE BITLINE BOOST SCHEME FOR SRAM WRITE-ASSIST - A device includes a transistor switch coupled between a bit line voltage node and a ground node and a boost signal circuit coupled to a gate node of the transistor switch, where the boost signal circuit providing a boost signal responsive to a write enable signal. The device also includes a first delay element and a first capacitor in series with the first delay element. The first capacitor has a first end coupled to the bit line voltage node and a second end coupled to the gate node through the first delay element. | 05-14-2015 |
20150248923 | MEMORY READING CIRCUIT, MEMORY DEVICE AND METHOD OF OPERATING MEMORY DEVICE - A circuit for reading a memory device includes a sense amplifier (SA) and a controller. The SA has an input, an output and an enabling terminal. The controller has a first input coupled to the output of the SA, a second input configured to receive a control signal, and an output coupled to the enabling terminal of the SA to send an SA enabling (SAE) signal from the controller to the SA. The controller is configured to start the SAE signal, in response to the control signal, to enable the SA, and to terminate the SAE signal, in response to an SA output signal at the output of the SA, to disable the SA. | 09-03-2015 |
20150262655 | NEGATIVE BITLINE BOOST SCHEME FOR SRAM WRITE-ASSIST - A device includes a transistor switch coupled between a bit line voltage node and a ground node and a boost signal circuit coupled to a gate node of the transistor switch, where the boost signal circuit providing a boost signal responsive to a write enable signal. The device also includes a first delay element and a first capacitor in series with the first delay element. The first capacitor has a first end coupled to the bit line voltage node and a second end coupled to the gate node through the first delay element. | 09-17-2015 |
20150269991 | MEMORY UNIT AND METHOD OF TESTING THE SAME - A memory unit that includes a tracking unit, a scan chain and a scan chain control unit. The tracking unit includes a tracking bit line, wherein the tracking unit is configured to receive a tracking control signal, selectively charge or discharge a voltage on the tracking bit line in response to the tracking control signal and generate a sense amplifier signal. The scan chain includes one or more logic devices, wherein the scan chain is configured to receive at least a first control signal. The scan chain control unit is connected to the scan chain and the tracking unit. The scan chain control unit is configured to receive the sense amplifier signal and generate the first scan chain control signal. | 09-24-2015 |