Patent application number | Description | Published |
20130270336 | SUPPLY ORDERING SYSTEM AND METHOD - A system and method for ordering supplies, includes a portable barcode scanner configured to output data according to at least one of an HID, CDC or SPP protocol. A mobile phone device incapable of recognizing and parsing data when the data is configured according to the HID, CDC or SPP protocol is connected to the scanner using a communication connection. A scanner adapter application on the mobile phone device, which receives the output data comprising order data, is configured to parse the order data and pass it to an upload application having a current data field that receives at least part of the order data. A listener server configured to receive the at least part of the order data from the upload application processes the order information into an electronic order, and sends the electronic order to a vendor server. | 10-17-2013 |
20130292465 | SUPPLY ORDERING SYSTEM AND METHOD - A system and method for ordering supplies, includes a portable barcode scanner configured to output data according to at least one of an HID, CDC or SPP protocol. A mobile phone device incapable of recognizing and parsing data when the data is configured according to the HID, CDC or SPP protocol is connected to the scanner using a communication connection. A scanner adapter application on the mobile phone device, which receives the output data comprising order data, is configured to parse the order data and pass it to an upload application having a current data field that receives at least part of the order data. A listener server configured to receive the at least part of the order data from the upload application processes the order information into an electronic order, and sends the electronic order to a vendor server. | 11-07-2013 |
Patent application number | Description | Published |
20110317894 | PROJECTION TRUNCATION PROCESSING FOR CBCT - A method for 3-D volume image reconstruction of a subject. 2-D projection images are obtained over a range of scan angles, and one or more truncated images are identified from the obtained images. From each of the one or more truncated images, a corrected truncated image is formed by a repeated process of identifying a row of image data values in the one or more truncated images, assigning an extension length to one or both ends of the row according to the row location in the truncated image, and extending the truncated image data for the row of image data values by applying a row-dependent cosine function to each value in the extension length. A 3-D volume image is reconstructed using one or more of the corrected truncated images. | 12-29-2011 |
20130004041 | METHODS AND APPARATUS FOR TEXTURE BASED FILTER FUSION FOR CBCT SYSTEM AND CONE-BEAM IMAGE RECONSTRUCTION - Embodiments of methods and/or apparatus for 3-D volume image reconstruction of a subject, executed at least in part on a computer for use with a digital radiographic apparatus can obtain a 3D volume reconstruction or projection image by generating a first-filtered set of projection images from a plurality of 2-D projection images taken over a range of scan angles and a different second-filtered set of projection images from the plurality of 2-D projection images. Then, for example, a first 3-D volume image of the subject from the first-filtered set of projection images and a second 3-D volume image of the subject from the second-filtered set of projection images can be combined using different weighting combinations in at least two corresponding portions to generate the 3-D volume image of the subject. | 01-03-2013 |
20130004042 | METHODS AND APPARATUS FOR SCATTER CORRECTION FOR CBCT SYSTEM AND CONE-BEAM IMAGE RECONSTRUCTION - Embodiments of methods and/or apparatus for 3-D volume image reconstruction of a subject, executed at least in part on a computer for use with a digital radiographic apparatus, can obtain image data for 2-D projection images over a range of scan angles. For each of the plurality of projection images, an enhanced projection image can be generated. In one embodiment, a first scatter intensity distribution through the plurality of projection images can be modulated based on a first scaling function and a SPR to generate a second scatter intensity distribution through the plurality of projection images, which can be combined with the original plurality of projection images. | 01-03-2013 |
20130051519 | METHODS AND APPARATUS FOR SUPER RESOLUTION SCANNING FOR CBCT SYSTEM AND CONE-BEAM IMAGE RECONSTRUCTION - Embodiments of methods and/or apparatus for 3-D volume image reconstruction of a subject, executed at least in part on a computer for use with a digital radiographic apparatus can obtain image data for 2-D projection images over a range of scan angles. For each of the plurality of projection images, an enhanced projection image can be generated. In one embodiment, through the application of a resolution increasing interpolator, a prescribed CBCT routine scanning mode with preset binning can increase a spatial resolution, Nyquist frequency or MTF. | 02-28-2013 |
20130259193 | APPARATUS AND METHOD FOR BREAST IMAGING - An apparatus for imaging a breast of a patient has a gantry with a radiation source and a sensor, the source and sensor rotatable in an arcuate orbit about a central axis and within a plane of revolution, wherein the arcuate orbit spans more than 180 degrees and less than 360 degrees, and wherein the gantry has a gantry cover that is disposed to be in contact with at least the chest wall of the patient. The gantry cover has a central opening about the central axis for insertion of the breast that is to be imaged and a peripheral cutout portion that defines the end-points of the arcuate orbit and that provides a space for positioning a portion of the patient's anatomy. | 10-03-2013 |
Patent application number | Description | Published |
20100016024 | Mobile Communications Device Diversity Antenna - A device including a battery, a wireless transceiver, and a battery cover. The battery cover is adapted to retain the battery in a desired position. The battery cover is further adapted to act as a first antenna in communication with the wireless transceiver for sending and receiving signals in a first frequency band. | 01-21-2010 |
20100103064 | PARASITIC DIPOLE ASSISTED WLAN ANTENNA - A parasitic dipole assisted WLAN antenna for creating a second resonance in the A band and providing greater bandwidth usage to a mobile computing or communication device. A secondary B/G band monopole antenna is connected to the A band antenna at the point of maximum impedance of the A band providing minimal interference between the two bands. The dipole structure antennas are connected at the A band loop antenna feed pin and ground pin. | 04-29-2010 |
20110140977 | COMPACT DUAL-MODE UHF RFID READER ANTENNA SYSTEMS AND METHODS - The present disclosure relates to compact, dual-mode ultra high frequency (UHF) radio frequency identification (RFID) reader antenna systems and methods capable of supporting both long range and short range applications. The present invention includes a dual-mode antenna design, a dual-mode RFID reader utilizing the dual-mode antenna design, and an associated usage method. The dual-mode antenna design may include a patch operating mode for long range applications and a slot operating mode for short range applications. Additionally, the dual-mode antenna design may include mechanisms to improve the patch operating mode bandwidth, circular polarization in the patch operating mode, and dual polarization in the slot operation mode. | 06-16-2011 |
Patent application number | Description | Published |
20080316709 | Thermally Conductive Electrical Structure and Method - An electrical structure and method of forming. The electrical structure includes a first substrate comprising a plurality of electrical components, a first thermally conductive film layer formed over and in contact with a first electrical component of the plurality of electrical components, a first thermally conductive structure in mechanical contact with a first portion of the first thermally conductive film layer, and a first thermal energy extraction structure formed over the first thermally conductive structure. The first thermal energy extraction structure is in thermal contact with the first thermally conductive structure. The first thermal energy extraction structure is configured to extract a first portion of thermal energy from the first electrical component through the first thermally conductive film layer and the first thermally conductive structure. | 12-25-2008 |
20090085151 | SEMICONDUCTOR FUSE STRUCTURE AND METHOD - An electrical structure and method of forming. The electrical structure includes a semiconductor substrate, an insulator layer formed over and in contact with the semiconductor substrate, and a semiconductor fuse structure formed over the insulator layer. The fuse structure includes a silicon layer and a continuous metallic silicide layer. The continuous metallic silicide layer includes a first section formed over and in contact with a first horizontal section of a top surface of the silicon layer, a second section formed over and in contact with a second horizontal section of the top surface of the silicon layer, and a third section formed within an opening within the top surface of the silicon layer. | 04-02-2009 |
20090090994 | ELECTROMIGRATION FUSE AND METHOD OF FABRICATING SAME - Fuses and methods of forming fuses. The fuse includes: a dielectric layer on a semiconductor substrate; a cathode stack on the dielectric layer, a sidewall of the cathode stack extending from a top surface of the cathode stack to a top surface of the dielectric layer; a continuous polysilicon layer comprising a cathode region, an anode region, a link region between the cathode and anode regions and a transition region between the cathode region and the link region, the transition region proximate to the sidewall of the cathode stack, the cathode region on a top surface of the cathode stack, the link region on a top surface of the dielectric layer, both a first thickness of the cathode region and a second thickness of the link region greater than a third thickness of the transition region; and a metal silicide layer on a top surface of the polysilicon layer. | 04-09-2009 |
20090108374 | HIGH DENSITY SRAM CELL WITH HYBRID DEVICES - Hybrid SRAM circuit, hybrid SRAM structures and method of fabricating hybrid SRAMs. The SRAM structures include first and second cross-coupled inverters coupled to first and second pass gate devices. The pull-down devices of the inverters are FinFETs while the pull-up devices of the inverters and the pass gate devices are planar FETs or pull-down and pull-up devices of the inverters are FinFETs while the pass gate devices are planar FETs. | 04-30-2009 |
20100012950 | CRACKSTOP STRUCTURES AND METHODS OF MAKING SAME - An integrated circuit chip and a method of fabricating an integrated circuit chip. The integrated circuit chip includes: a set of wiring levels stacked from a first wiring level to a last wiring level; and a respective void in each wiring level of two or more wiring levels of the set wiring levels, each respective void extending in a continuous ring parallel and proximate to a perimeter of the integrated circuit chip, a void of a higher wiring level stacked directly over but not contacting a void of a lower wiring level, the respective voids forming a crack stop. | 01-21-2010 |
20100013043 | CRACKSTOP STRUCTURES AND METHODS OF MAKING SAME - An integrated circuit chip and a method of fabricating an integrated circuit chip. The integrated circuit chip includes: a continuous first stress ring proximate to a perimeter of the integrated circuit chip, respective edges of the first stress ring parallel to respective edges of the integrated circuit chip; a continuous second stress ring between the first stress ring and the perimeter of the integrated circuit chip, respective edges the second stress ring parallel to respective edges of the integrated circuit chip, the first and second stress rings having opposite internal stresses; a continuous gap between the first stress ring and the second stress ring; and a set of wiring levels from a first wiring level to a last wiring level on the substrate. | 01-21-2010 |
Patent application number | Description | Published |
20090049897 | METHOD FOR ON-LINE ADAPTATION OF ENGINE VOLUMETRIC EFFICIENCY USING A MASS AIR FLOW SENSOR - An electronic engine controller is configured to execute a process of adapting a base value of the volumetric efficiency of an engine through the addition of a correction value of the volumetric efficiency. The process includes comparing an estimated mass air flow value calculated using a speed-density equation, with an actual mass air flow value measured by a mass air flow (MAF) sensor. A percentage error of the estimated mass air flow value as compared to the actual mass air flow value is calculated. When the percentage error indicates that the air flow is at steady state, then the process updates the VE correction value, by integrating the percentage error. The new correction value, thus computed, is then stored in a cell of an array corresponding to the current engine operating condition. The process is configured to add the correction value to the corresponding base value to produce an updated value of the VE, valid for that operating condition. The process accommodates changes in the volumetric efficiency of the engine due to part aging and deposit build-up over time, among other things. The updated VE value may then be used for mass air flow estimation and accordingly for fueling control as well. | 02-26-2009 |
20090182489 | INTAKE AIR TEMPERATURE (IAT) RATIONALITY DIAGNOSTIC WITH AN ENGINE BLOCK HEATER - A first method is suitable for vehicles having an ambient temperature sensor and employs an estimation model configured to estimate a minimum start-up engine coolant temperature (SUECT) if the engine block heater was operated during the previous soak period. A measured SUECT is then compared to estimated minimum SUECT from the model, and if it is higher, then the diagnostic logic concludes that the engine block heater was operated during the soak period, and disables the reporting its test results. A second method is suitable for vehicles without an ambient (soak) temperature sensor employs an alternative approach. Predetermined data based on actual vehicle testing over a wide range of conditions is stored in a data structure. The data describe respective minimum and maximum start-up IAT thresholds versus SUECT. The thresholds are spaced apart to define a start-up IAT window in between. In other words, the window is bounded by minimum and maximum start-up IAT thresholds. For any measured SUECT, a particular window will be set. If the measured start-up IAT falls within the window, then the engine block heater was operated during the soak period. | 07-16-2009 |
Patent application number | Description | Published |
20090305414 | Methods Of Tissue Engineering - An improved substrate for growing mono-layers of adherent-type cells and methods of growing tissue structures, ex vivo. The improved substrate, which comprises a silicon substrate coated with a photo cleavable polymer, releases adherent cells non-enzymatically. Also disclosed are methods for assembling complex layers of cells of various types. | 12-10-2009 |
20090314998 | SYNTHESIS OF POLYMER NANOSTRUCTURES WITH CONDUCTANCE SWITCHING PROPERTIES - The present invention is directed to crystalline organic polymer nanoparticles comprising a conductive organic polymer; wherein the crystalline organic polymer nanoparticles have a size of from 10 nm to 200 nm and exhibits two current-voltage states: (1) a high resistance current-voltage state, and (2) a low resistance current-voltage state, wherein when a first positive threshold voltage (V | 12-24-2009 |
20100119827 | POLYMER SUBMICRON PARTICLE PREPARATION BY SURFACTANT-MEDIATED PRECIPITATION - The present invention is directed to methods for the fabrication of polymer nanoparticles comprising the addition polymer solutions to aqueous solutions containing surfactants, wherein the concentration of the surfactants in the aqueous solution are lower than the critical micelle concentration of the surfactants. The methods of the present invention provide for the precipitation of uniformly dispersed polymer particles in the submicron size range, preferably from about 5 nm to about 100 nm. | 05-13-2010 |
20100171063 | PREPARATION OF PEROVSKITE NANOCRYSTALS VIA REVERSE MICELLES - The present invention is directed to perovskite nanostructures of Formula ABO | 07-08-2010 |
20100288964 | Multiferroic Nanoscale Thin Film Materials, Method of its Facile Syntheses and Magnetoelectric Coupling at Room Temperature - Methods of producing a multiferroic thin film material. The method includes the steps of providing a multiferroic precursor solution, subjecting the precursor solution to spin casting to produce a spin cast film, and heating the spin cast film. The precursor solution may include Bi(NO | 11-18-2010 |
Patent application number | Description | Published |
20110104799 | Multifunctional Alleles - Nucleic acid constructs and methods for rendering modifications to a genome are provided, wherein the modifications comprise null alleles, conditional alleles and null alleles comprising COINs. Multifunctional alleles (MFA) are provided, as well as methods for making them, which afford the ability in a single targeting to introduce an allele that can be used to generate a null allele, a conditional allele, or an allele that is a null allele and that further includes a COIN. MFAs comprise pairs of cognate recombinase recognition sites, an actuating sequence and/or a drug selection cassette, and a nucleotide sequence of interest, and a COIN, wherein upon action of a recombinase a conditional allele with a COIN is formed. In a further embodiment, action of a second recombinase forms an allele that contains only a COIN in sense orientation. In a further embodiment, action by a third recombinase forms an allele that contains only the actuating sequence in sense orientation. | 05-05-2011 |
20130302899 | MULTIFUNCTIONAL ALLELES - Nucleic acid constructs and methods for rendering modifications to a genome are provided, wherein the modifications comprise null alleles, conditional alleles and null alleles comprising COINs. Multifunctional alleles (MFA) are provided, as well as methods for making them, which afford the ability in a single targeting to introduce an allele that can be used to generate a null allele, a conditional allele, or an allele that is a null allele and that further includes a COIN. MFAs comprise pairs of cognate recombinase recognition sites, an actuating sequence and/or a drug selection cassette, and a nucleotide sequence of interest, and a COIN, wherein upon action of a recombinase a conditional allele with a COIN is formed. In a further embodiment, action of a second recombinase forms an allele that contains only a COIN in sense orientation. In a further embodiment, action by a third recombinase forms an allele that contains only the actuating sequence in sense orientation. | 11-14-2013 |
Patent application number | Description | Published |
20080242070 | INTEGRATION SCHEMES FOR FABRICATING POLYSILICON GATE MOSFET AND HIGH-K DIELECTRIC METAL GATE MOSFET - Multiple integration schemes for manufacturing dual gate semiconductor structures are disclosed. By employing the novel integration schemes, polysilicon gate MOSFETs and high-k dielectric metal gate MOSFETs are formed on the same semiconductor substrate despite differences in the composition of the gate stack and resulting differences in the etch rates. A thin polysilicon layer is used for one type of gate electrodes and a silicon-containing layer are used for the other type of gate electrodes in these integration schemes to balance the different etch rates and to enable etching of the two different gate stacks. | 10-02-2008 |
20100252810 | GATE PATTERNING OF NANO-CHANNEL DEVICES - Methodologies and gate etching processes are presented to enable the fabrication of gate conductors of semiconductor devices, such as NFETs and/or PFETs, which are equipped with nano-channels. In one embodiment, a sacrificial spacer of equivalent thickness to the diameter of the gate nano-channel is employed and is deposited after patterning the gate conductor down to the gate dielectric. The residue gate material that is beneath the nano-channel is removed utilizing a medium to high density, bias-free, fluorine-containing or fluorine- and chlorine-containing isotropic etch process without compromising the integrity of the gate. In another embodiment, an encapsulation/passivation layer is utilized. In yet further embodiment, no sacrificial spacer or encapsulation/passivation layer is used and gate etching is performed in an oxygen and nitrogen-free ambient. | 10-07-2010 |
20110006367 | GATE PATTERNING OF NANO-CHANNEL DEVICES - Methodologies and gate etching processes are presented to enable the fabrication of gate conductors of semiconductor devices, such as NFETs and/or PFETs, which are equipped with nano-channels. In one embodiment, a sacrificial spacer of equivalent thickness to the diameter of the gate nano-channel is employed and is deposited after patterning the gate conductor down to the gate dielectric. The residue gate material that is beneath the nano-channel is removed utilizing a medium to high density, bias-free, fluorine-containing or fluorine- and chlorine-containing isotropic etch process without compromising the integrity of the gate. In another embodiment, an encapsulation/passivation layer is utilized. In yet further embodiment, no sacrificial spacer or encapsulation/passivation layer is used and gate etching is performed in an oxygen and nitrogen-free ambient. | 01-13-2011 |
20120256278 | Method of Removing High-K Dielectric Layer on Sidewalls of Gate Structure - A semiconductor structure, and method of forming a semiconductor structure, that includes a gate structure on a semiconductor substrate, in which the gate structure includes a gate conductor and a high-k gate dielectric layer. The high-k gate dielectric layer is in contact with the base of the gate conductor and is present on the sidewalls of the gate conductor for a dimension that is less than ¼ the gate structure's height. The semiconductor structure also includes source regions and drain regions present in the semiconductor substrate on opposing sides of the gate structure. | 10-11-2012 |
20140070316 | REPLACEMENT SOURCE/DRAIN FOR 3D CMOS TRANSISTORS - A method of forming a semiconductor structure may include forming at least one fin and forming, over a first portion of the at least one fin structure, a gate. Gate spacers may be formed on the sidewalls of the gate, whereby the forming of the spacers creates recessed regions adjacent the sidewalls of the at least one fin. A first epitaxial region is formed that covers both one of the recessed regions and a second portion of the at least one fin, such that the second portion extends outwardly from one of the gate spacers. A first epitaxial layer is formed within the one of the recessed regions by etching the first epitaxial region and the second portion of the at least one fin. A second epitaxial region is formed at a location adjacent one of the spacers and over the first epitaxial layer within one of the recessed regions. | 03-13-2014 |
Patent application number | Description | Published |
20080246388 | INFRARED DISPLAY WITH LUMINESCENT QUANTUM DOTS - A display device that includes an underlying excitation source, a converting layer, and an optical filter layer. The underlying excitation source emits light in a spatial pattern that may or may not be altered in time and has a short wavelength capable of being at least partially absorbed by the overlying converting layer. The converting layer can be a contiguous film or pixels of quantum dots that can be dispersed in a matrix material. This converting layer is capable of absorbing at least a portion of the wavelength(s) of the light from the underlying excitation source and emitting light at one or more different wavelengths. The optical filter layer prevents the residual light from the excitation source that was not absorbed by the converting layer from being emitted by the display device. | 10-09-2008 |
20080277626 | QUANTUM DOT FLUORESCENT INKS - The present invention relates to inks and more particularly, to fluorescent ink formulations including quantum dots for various printing processes such as inkjet, flexographic, screen printing, thermal transfer, and pens. The inks include one or more populations of fluorescent quantum dots dispersed in polymeric material, having fluorescence emissions between about 450 nm and about 2500 nm; and a liquid or solid vehicle. The vehicle is present in a ratio to achieve an ink viscosity, surface tension effective, drying time and other printing parameters used for printing processes. | 11-13-2008 |
20100109521 | QUANTUM DOT ELECTROLUMINESCENT DEVICE - An EL device is presented which consists of a simple three active layer construction. A layer of a dielectric material, a traditional EL phosphor layer, and a quantum dot layer are present between an electrode and a transparent electrode. The EL device is operated efficiently by an AC source. Quantum dots which emit in the visible spectrum are used. The EL device is fully color tunable by altering the composition and thickness of the layers. | 05-06-2010 |
20100270511 | NANOSTRUCTURED LAYERS, METHODS OF MAKING NANOSTRUCTURED LAYERS, AND APPLICATION THEREOF - One embodiment of the invention provides a nanostructure layer, comprising: a first population of semiconductor nanocrystals forming electron transport conduits; a second population of semiconductor nanocrystals forming hole transport conduits; and a third population of semiconductor nanocrystals capable of at least one of the following: absorbing light or emitting light. | 10-28-2010 |
Patent application number | Description | Published |
20130073675 | MANAGING RELATED DIGITAL CONTENT - Aspects of the present disclosure relate to one or more configured computing systems identifying companion content and supplemental content for a base content. Companion content may include, for example, video adaptations of the base content. Supplemental content may include content referenced or related in subject matter to the base content. Information regarding companion content may be utilized to enable a user to interchangeably or synchronously present either a base content (e.g., an eBook or audio book) with the companion content (e.g., a movie adaptation). Information regarding supplemental content may be utilized to present the supplemental content during consumption of a base content, or to save supplemental content for later viewing. | 03-21-2013 |
20130074133 | MANAGING RELATED DIGITAL CONTENT - Aspects of the present disclosure relate to one or more configured computing systems identifying companion content and supplemental content for a base content. Companion content may include, for example, video adaptations of the base content. Supplemental content may include content referenced or related in subject matter to the base content. Information regarding companion content may be utilized to enable a user to interchangeably or synchronously present either a base content (e.g., an eBook or audio book) with the companion content (e.g., a movie adaptation). Information regarding supplemental content may be utilized to present the supplemental content during consumption of a base content, or to save supplemental content for later viewing. | 03-21-2013 |
20130257871 | Content Customization - A content processing service may analyze an item of original content and identify several objects, attributes of those objects, and relationships between those objects present in the item of original content. The content processing service may also analyze a source graph, such as a social graph or supplemental graph, and identify several objects, attributes of those objects, and relationships between those objects present in the source graph. The content processing service may customize the item of original content by selecting an original object and selecting a source graph object. One or more of the attributes or relationships of the selected original object in the item of original content may be replaced by one or more of the attributes or relationships of the selected source graph object, thereby forming an item of modified content. | 10-03-2013 |
20130262127 | Content Customization - A content processing service may analyze an item of original content and identify several objects, attributes of those objects, and relationships between those objects present in the item of original content. The content processing service may also analyze a source graph, such as a social graph or supplemental graph, and identify several objects, attributes of those objects, and relationships between objects present in the source graph. The content processing service may customize the item of original content by selecting an original object and selecting a source graph object. One or more of the attributes or relationships of the selected original object in the item of original content may be replaced by one or more of the attributes or relationships of the selected source graph object. To customize items of audio content, audio content associated with the source graph object may replace audio content associated with the target graph object. | 10-03-2013 |
20140005814 | PACING CONTENT | 01-02-2014 |
20140122564 | MANAGING USE OF A SHARED CONTENT CONSUMPTION DEVICE - Features are disclosed for identifying multiple users contending for use of a shared media device with which to present a content item. Users may be detected by the shared media device or a management component, and each user may have previously begun and stopped consumption at a different point within the content item. When multiple users wish to consume the content, a component or module determines which presentation position to use, or creates a new presentation position for use. In cases in which not all users have begun consuming or wish to consume the same content item, a component or module determines which content item to present. | 05-01-2014 |
Patent application number | Description | Published |
20130005103 | METHODS FOR FABRICATING A FINFET INTEGRATED CIRCUIT ON A BULK SILICON SUBSTRATE - Methods are provided for fabricating a FINFET integrated circuit that includes epitaxially growing a first silicon germanium layer and a second silicon layer overlying a silicon substrate. The second silicon layer is etched to form a silicon fin using the first silicon germanium layer as an etch stop. The first silicon germanium layer underlying the fin is removed to form a void underlying the fin and the void is filled with an insulating material. A gate structure is then formed overlying the fin. | 01-03-2013 |
20130032890 | SELF-ADJUSTING LATCH-UP RESISTANCE FOR CMOS DEVICES - CMOS devices ( | 02-07-2013 |
20130049142 | TRANSISTOR WITH REDUCED PARASITIC CAPACITANCE - Scaled transistors with reduced parasitic capacitance are formed by replacing a high-k dielectric sidewall spacer with a SiO | 02-28-2013 |
20130181260 | METHOD FOR FORMING N-SHAPED BOTTOM STRESS LINER - Semiconductor devices with n-shaped bottom stress liners are formed. Embodiments include forming a protuberance on a substrate, conformally forming a sacrificial material layer over the protuberance, forming a gate stack above the sacrificial material layer on a silicon layer, removing the sacrificial material layer to form a tunnel, and forming a stress liner in the tunnel conforming to the shape of the protuberance. Embodiments further include forming a silicon layer over the sacrificial material layer and lining the tunnel with a passivation layer prior to forming the stress liner. | 07-18-2013 |
20130224945 | METHODS OF FORMING BULK FINFET DEVICES WITH REPLACEMENT GATES SO AS TO REDUCE PUNCH THROUGH LEAKAGE CURRENTS - One illustrative method disclosed herein includes forming a plurality of spaced-apart trenches in a semiconducting substrate to thereby define a fin structure for the device, forming a local isolation region within each of the trenches, forming a sacrificial gate structure on the fin structure, wherein the sacrificial gate structure comprises at least a sacrificial gate electrode, and forming a layer of insulating material above the fin structure and within the trench above the local isolation region. In this example, the method further includes performing at least one etching process to remove the sacrificial gate structure to thereby define a gate cavity, after removing the sacrificial gate structure, performing at least one etching process to form a recess in the local isolation region, and forming a replacement gate structure that is positioned in the recess in the local isolation region and in the gate cavity. | 08-29-2013 |
20140015020 | METHOD FOR FORMING N-SHAPED BOTTOM STRESS LINER - Semiconductor devices with n-shaped bottom stress liners are formed. Embodiments include forming a protuberance on a substrate, conformally forming a sacrificial material layer over the protuberance, forming a gate stack above the sacrificial material layer on a silicon layer, removing the sacrificial material layer to form a tunnel, and forming a stress liner in the tunnel conforming to the shape of the protuberance. Embodiments further include forming a silicon layer over the sacrificial material layer and lining the tunnel with a passivation layer prior to forming the stress liner. | 01-16-2014 |
20140120708 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES INCLUDING REPLACEMENT METAL GATE PROCESS INCORPORATING A CONDUCTIVE DUMMY GATE LAYER - A method of manufacturing a semiconductor device including a replacement metal gate process incorporating a conductive dummy gate layer (e.g., silicon germanium (SiGe), titanium nitride, etc.) and a related are disclosed. The method includes forming an oxide layer on a substrate; removing a gate portion of the oxide layer from the substrate in a first region of the semiconductor device; forming a conductive dummy gate layer on the semiconductor device in the first region; and forming a gate on the semiconductor device, the gate including a gate conductor disposed in the first region and directly connected to the substrate. | 05-01-2014 |
20140159052 | METHOD AND STRUCTURE FOR TRANSISTOR WITH REDUCED DRAIN-INDUCED BARRIER LOWERING AND ON RESISTANCE - Embodiments of the invention provide an improved method and structure for a transistor with reduced DIBL and R | 06-12-2014 |
20140264613 | INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH ACTIVE AREA PROTECTION - Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a semiconductor substrate includes a shallow trench isolation structure disposed therein. A gate electrode structure overlies semiconductor material of the semiconductor substrate. A first sidewall spacer is formed adjacent to the gate electrode structure, with a first surface of the shallow trench isolation structure exposed and spaced from the first sidewall spacer by a region of the semiconductor material. The first surface of the shallow trench isolation structure is masked with an isolation structure mask. The region of the semiconductor material is free from the isolation structure mask. A recess is etched in the region of the semiconductor material, with the isolation structure mask in place. A semiconductor material is epitaxially grown within the recess to form an epitaxially-grown semiconductor region adjacent to the gate electrode structure. | 09-18-2014 |
20150021702 | SHALLOW TRENCH ISOLATION - A semiconductor structure with an improved shallow trench isolation (STI) region and method of fabrication is disclosed. The STI region comprises a lower portion filled with oxide and an upper portion comprising a high Young's modulus (HYM) liner disposed on the lower portion and trench sidewalls and filled with oxide. The HYM liner is disposed adjacent to source-drain regions, and serves to reduce stress relaxation within the shallow trench isolation (STI) oxide, which has a relatively low Young's modulus and is soft. Hence, the HYM liner serves to increase the desired stress imparted by the embedded stressor source-drain regions, which enhances carrier mobility, thus increasing semiconductor performance. | 01-22-2015 |
Patent application number | Description | Published |
20100210624 | ARYLOXY- AND HETEROARYLOXY-SUBSTITUTED TETRAHYDROBENZAZEPINES AND USE THEREOF TO BLOCK REUPTAKE OF NOREPINEPHRINE, DOPAMINE, AND SEROTONIN - The aryloxy- and heteroaryloxy-substituted tetrahydrobenzazepine derivative compounds of the present invention are represented by formulae (I) (A-E) having the following structure where the carbon atom designated * is in the R or S configuration and the substituents X and R | 08-19-2010 |
20110077400 | PROCESSES FOR PREPARING TETRAHYDROISOQUINOLINES - Disclosed are processes for preparing tetrahydroisoquinolines, intermediates useful in the preparation of tetrahydroisoquinolines, processes for preparing such intermediates, and a crystalline form of 6-[(4S)-2-methyl-4-(naphthyl)-1,2,3,4-tetrahydroisoquinolin-7-yl]pyridazin-3-amine. Also disclosed are pharmaceutical compositions comprising tetrahydroisoquinolines, methods of using tetrahydroisoquinolines in the treatment of depression and other conditions and methods for obtaining the crystalline form. | 03-31-2011 |
20110160220 | CRYSTALLINE FORM OF 6-[(4S)-2-METHYL-4-(2-NAPHTHYL)-1,2,3,4-TETRAHYDROISOQUINOLIN-7-YL]PYRIDA- ZIN-3-AMINE - The present disclosure generally relates to a crystalline form of 6-[(4S)-2-methyl-4-(naphthyl)-1,2,3,4-tetrahydroisoquinolin-7-yl]pyridazin-3-amine. The present disclosure also generally relates to pharmaceutical compositions comprising the crystalline form, as well of methods of using a crystalline form in the treatment of depression and other conditions and methods for obtaining such crystalline form. | 06-30-2011 |
Patent application number | Description | Published |
20090190413 | SELF-REPAIR INTEGRATED CIRCUIT AND REPAIR METHOD - A method for repairing degraded field effect transistors includes forward biasing PN junctions of one of a source and a drain of a field effect transistor (FET), and a body of the FET. Charge is injected from a substrate to a gate region to neutralize charge in the gate region. The method is applicable to CMOS devices. Repair circuits are disclosed for implementing the repairs. | 07-30-2009 |
20090200598 | FLASH MEMORY STRUCTURE WITH ENHANCED CAPACITIVE COUPLING COEFFICIENT RATIO (CCCR) AND METHOD FOR FABRICATION THEREOF - A flash memory structure having an enhanced capacitive coupling coefficient ratio (CCCR) may be fabricated in a self-aligned manner while using a semiconductor substrate that has an active region that is recessed within an aperture with respect to an isolation region that surrounds the active region. The flash memory structure includes a floating gate that does not rise above the isolation region, and that preferably consists of a single layer that has a U shape. The U shape facilitates the enhanced capacitive coupling coefficient ratio. | 08-13-2009 |
20090243738 | MULTIPLE STATUS E-FUSE BASED NON-VOLATILE VOLTAGE CONTROL OSCILLATOR CONFIGURED FOR PROCESS VARIATION COMPENSATION, AN ASSOCIATED METHOD AND AN ASSOCIATED DESIGN STRUCTURE - Disclosed are embodiments of a voltage controlled oscillator (VCO) capable of non-volatile self-correction to compensate for process variations and to ensure that the center frequency of the oscillator is maintained within a predetermined frequency range. This VCO incorporates a pair of varactors connected in parallel to an inductor-capacitor (LC) tank circuit for outputting a periodic signal having a frequency that is proportional to an input voltage. A control loop uses a programmable variable resistance e-fuse to set a compensation voltage to be applied to the pair of varactors. By adjusting the compensation voltage, the capacitance of the pair of varactors can be adjusted in order to selectively increase or decrease the frequency of the periodic signal in response to a set input voltage and, thereby to bring the frequency of that periodic signal into the predetermined frequency range. Also disclosed are embodiments of an associated design structure for such a VCO and an associated method for operating such a VCO. | 10-01-2009 |
20090243739 | MULTIPLE STATUS E-FUSE BASED NON-VOLATILE VOLTAGE CONTROL OSCILLATOR CONFIGURED FOR PROCESS VARIATION COMPENSATION, AN ASSOCIATED METHOD AND AN ASSOCIATED DESIGN STRUCTURE - Disclosed are embodiments of a voltage controlled oscillator (VCO) capable of non-volatile self-correction to compensate for process variations and to ensure that the center frequency of the oscillator is maintained within a predetermined frequency range. This VCO incorporates a pair of varactors connected in parallel to an inductor-capacitor (LC) tank circuit for outputting a periodic signal having a frequency that is proportional to an input voltage. A control loop uses a programmable variable resistance e-fuse to set a compensation voltage to be applied to the pair of varactors. By adjusting the compensation voltage, the capacitance of the pair of varactors can be adjusted in order to selectively increase or decrease the frequency of the periodic signal in response to a set input voltage and, thereby to bring the frequency of that periodic signal into the predetermined frequency range. Also disclosed are embodiments of an associated design structure for such a VCO and an associated method for operating such a VCO. | 10-01-2009 |
20100210043 | IN-LINE DEPTH MEASUREMENT OF THRU SILICON VIA - A system, method and device for measuring a depth of a Through-Silicon-Via (TSV) in a semiconductor device region on a wafer during in-line semiconductor fabrication, includes a resistance measurement trench structure having length and width dimensions in a substrate, ohmic contacts on a surface of the substrate disposed on opposite sides of the resistance measurement trench structure, and an unfilled TSV structure in semiconductor device region having an unknown depth. A testing circuit makes contact with the ohmic contacts and measures a resistance therebetween, and a processor connected to the testing circuit calculates a depth of the trench structure and the unfilled TSV structure based on the resistance measurement. The resistance measurement trench structure and the unfilled TSV are created simultaneously during fabrication. | 08-19-2010 |
20120184076 | FLASH MEMORY STRUCTURE WITH ENHANCED CAPACITIVE COUPLING COEFFICIENT RATIO (CCCR) AND METHOD FOR FABRICATION THEREOF - A flash memory structure having an enhanced capacitive coupling coefficient ratio (CCCR) may be fabricated in a self-aligned manner while using a semiconductor substrate that has an active region that is recessed within an aperture with respect to an isolation region that surrounds the active region. The flash memory structure includes a floating gate that does not rise above the isolation region, and that preferably consists of a single layer that has a U shape. The U shape facilitates the enhanced capacitive coupling coefficient ratio. | 07-19-2012 |
20130223172 | SELF-REPAIR INTEGRATED CIRCUIT AND REPAIR METHOD - A method for repairing degraded field effect transistors includes forward biasing PN junctions of one of a source and a drain of a field effect transistor (FET), and a body of the FET. Charge is injected from a substrate to a gate region to neutralize charge in the gate region. The method is applicable to CMOS devices. Repair circuits are disclosed for implementing the repairs. | 08-29-2013 |