Yang, Ichon-Si
Chang Won Yang, Ichon-Si KR
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20120198180 | NONVOLATILE MEMORY SYSTEM AND FLAG DATA INPUT/OUTPUT METHOD FOR THE SAME - Various embodiments of a nonvolatile memory system and related methods are disclosed. In one exemplary embodiment, the memory system may include: a memory area including a main memory area and a flag memory area; and an input/output controller configured to receive main data through a main data input line and provide the received main data to a page buffer circuit in response to a main data input control signal. The input/output controller may be further configured to receive flag data through the main data input line and provide the received flag data to the page buffer circuit in response to a flag data input control signal. | 08-02-2012 |
Chul Woo Yang, Ichon-Si KR
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20120206975 | SEMICONDUCTOR MEMORY APPARATUS AND DATA ERASING METHOD - A data erasing method of a semiconductor memory apparatus may include: if any one threshold voltage of a plurality of memory cells, for which an erase operation has been performed using an erase voltage pulse, is higher than an erase verification voltage, increasing a voltage level of the erase verification voltage applied to a plurality of word lines of the plurality of memory cells until the threshold voltage of the plurality of memory cells is lower than the erase verification voltage, and increasing a voltage level of the erase voltage pulse by an increased voltage level of the erase verification voltage and applying the erase voltage pulse to the plurality of memory cells. | 08-16-2012 |
Hong-Seon Yang, Ichon-Si KR
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20090111254 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming an insulation layer over a substrate including a pattern for forming a multi-plane channel, forming a columnar polysilicon layer over the insulation layer and filling in the pattern, and performing a thermal treatment process. | 04-30-2009 |
Sun Suk Yang, Ichon-Si KR
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20100214865 | SEMICONDUCTOR MEMORY APPARATUS AND METHOD OF CONTROLLING THE SAME - A semiconductor memory apparatus includes: an address buffer configured to buffer an input address and generate a buffered address; a command buffer configured to buffer a chip selection command and generate a buffered command; a latch control unit configured to receive an internal clock and the buffered command and generate a latch control signal; and an address latch unit configured to latch the buffered address based on the latch control signal. | 08-26-2010 |
20120026809 | MULTI-BIT TEST CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - A multi-bit test circuit for a semiconductor memory is configured to cause an active command to activate active signals. At least two active signals are respectively inputted to a plurality of banks at different timings in a multi-bit test mode. | 02-02-2012 |
Wun-Mo Yang, Ichon-Si KR
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20100082917 | SOLID STATE STORAGE SYSTEM AND METHOD OF CONTROLLING SOLID STATE STORAGE SYSTEM USING A MULTI-PLANE METHOD AND AN INTERLEAVING METHOD - A solid state storage system includes a memory area configured to include a plurality of chips, and a micro controller unit (MCU) configured to perform a control operation, such that continuous logical block addresses are allocated using a multi-plane method or an interleaving method to different chips, and a read/write operation is performed in the logical block address unit in response to a read/write command. | 04-01-2010 |
20120017053 | NONVOLATILE MEMORY APPARATUS FOR PERFORMING WEAR-LEVELING AND METHOD FOR CONTROLLING THE SAME - Various embodiments of a nonvolatile memory apparatus are disclosed. In one exemplary embodiment, the nonvolatile memory apparatus may include: a host interface; a memory controller coupled to the host interface; and a memory area including a plurality of chips controlled by the memory controller. The memory controller may be configured to assign logical addresses to the plurality of chips to form a plurality of virtual logical groups, set a plurality of threshold values and a plurality of scan ranges depending on the total erase count (TEC) of each logical group, and perform wear-leveling in stages. | 01-19-2012 |
20120159280 | METHOD FOR CONTROLLING NONVOLATILE MEMORY APPARATUS - There is provided a method for controlling a nonvolatile memory apparatus in a nonvolatile memory system including a host interface, a memory controller, and a memory area. The method includes: checking a number of ECC fail bits, determining whether or not to replace a corresponding block, and replacing the block, while a read command provided from the host interface is performed; and replacing a block, which was not replaced during the read operation, with a block to be used as a replacement target during a write operation. | 06-21-2012 |
20120191897 | NON-VOLATILE MEMORY SYSTEM AND MANAGEMENT METHOD THEREOF - A non-volatile memory system includes a memory area including a plurality of non-volatile memory blocks, and a micro control unit configured to manage the memory blocks as a data block and a buffer block. As a write command is input, if no buffer block assigned to the data block exists and a free page exists in the data block, the micro control unit converts the data block to a self-buffer block. | 07-26-2012 |