Yadoguchi
Tetsuya Yadoguchi, Kitakyushu-Shi JP
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20110232386 | ULTRASONIC FLAW DETECTING APPARATUS AND ULTRASONIC FLAW DETECTING METHOD - According to one embodiment, An ultrasonic flaw detecting apparatus comprising: a transducer in which a piezoelectric element array for transmitting ultrasonic waves to and receiving echo signals from a test object; an element driving unit for scanning the piezoelectric element array at a predetermined cycle and causing the ultrasonic waves; a synthesizing unit for synthesizing an internal image of the test object based on the echo signals received by the piezoelectric element array; and a signal replacing unit for replacing the received echo signal with an echo signal in which a bottom echo of the test object is removed. | 09-29-2011 |
Tetsuya Yadoguchi, Chiyoda-Ku JP
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20130173508 | DEFECT CLASSIFICATION APPARATUS - The present invention has its objective to provide a defect classification apparatus which suppresses over-fitting and accurately classify the defect type of a defect. A defect classification apparatus is provided in which a data point indicating feature information of a defect to be classified having an unknown defect type is mapped to a point in a mapping space having a dimensional number higher than the number of features constituting the feature information, and the defect type of the defect to be classified is classified based on in which of two regions of defect type, which are formed by separating the mapping space by a decision boundary, the mapped point is located, wherein a discriminant function indicating the decision boundary is determined by adopting a weight which minimizes the sum of the classification error, which corresponds to the accuracy in classifying a training defect dataset, and a regularization term, which has a positive correlation with the dimensional number of the decision boundary, as the weight for each feature constituting the discriminant function. | 07-04-2013 |
Yasuhiro Yadoguchi, Kanagawa JP
Patent application number | Description | Published |
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20120274354 | LOGIC CIRCUIT DESIGN METHOD, LOGIC DESIGN PROGRAM, AND SEMICONDUCTOR INTEGRATED CIRCUIT - A computer device which performs logic synthesis using hardware description and a component in a cell library and generates a net list of a logic circuit including a series path of a clock synchronous sequential circuit and a combinational circuit performs optimization processing for decreasing the number of gate stages in a critical path between sequential circuits in the data path by using a third sequential circuit having a negative-logic input terminal and a negative-logic non-inverted output terminal and a fourth sequential circuit having a negative-logic input terminal and a negative-logic inverted output terminal in addition to a first sequential circuit having a positive-logic input terminal and a positive-logic non-inverted output terminal and a second sequential circuit having a positive-logic input terminal and a positive-logic inverted output terminal. | 11-01-2012 |