Patent application number | Description | Published |
20090016113 | NON-DIFFUSION JUNCTION SPLIT-GATE NONVOLATILE MEMORY CELLS AND ARRAYS, METHODS OF PROGRAMMING, ERASING, AND READING THEREOF, AND METHODS OF MANUFACTURE - Nonvolatile flash memory systems and methods are disclosed having a semiconductor substrate of a first conductivity type, including non-diffused channel regions through which electron flow is induced by application of voltage to associated gate elements. A plurality of floating gates are spaced apart from one another and each insulated from the channel region. A plurality of control gates are spaced apart from one another and insulated from the channel region, with each control gate being located between a first floating gate and a second floating gate and capacitively coupled thereto to form a subcell. A plurality of spaced-apart assist gates are insulated from the channel region, with each assist gate being located between and insulated from adjacent subcells. The channel is formed of three regions, two beneath adjacent control gate elements as well as a third region between the first two and beneath an associated assist gate. | 01-15-2009 |
20090290430 | Method And Apparatus For Reading And Programming A Non-Volatile Memory Cell In A Virtual Ground Array - A method and apparatus for dynamic programming and dynamic reading of a select non-volatile memory cell in a virtual grounds array is disclosed. The array of non-volatile memory cells are arranged in a plurality of rows and columns, wherein each cell in the same column share a first local bit line to one side and share a second local bit line to another side. Alternating local bit lines are connected to a first global bit line and other alternating local bit lines are connected to a second global bit line with the global bit lines connected to a sense amplifier. In the dynamic read operation the global bit lines and the associated local bit lines are connected to a precharged voltage. One of the first or second global bit lines is connected to a low voltage such as ground, wherein the one global bit line connected to ground also connects to the local bit line for sensing the select non-volatile memory cell. The state of the select non-volatile memory cell is detected by detecting the sense amplifier connected to the global bit line, other than the one global bit line. In a dynamic programming operation, the first and second global bit lines and their associated local bit lines are precharged to a first voltage. One of the first or second global bit line and its associated local bit lines is connected to a second voltage, wherein the associated local bit lines of the one global bit line include a select bit line connected to a programming terminal of the select non-volatile memory cell. The voltage differential between the second voltage and the first voltage is insufficient to cause programming of the select non-volatile memory cell. The bit line, other than the select bit line of the select non-volatile memory cell, is connected to a low voltage such as ground. The voltage differential between the second voltage and ground is sufficient to cause programming of the select non-volatile memory cell. In another embodiment of the programming operation, a local bit line connected to a programming terminal of a select non-volatile memory cell is precharged to a first voltage and then boosted to a programming voltage by precharging an adjacent local bit line. | 11-26-2009 |
20100200904 | GATE FRINGING EFFECT BASED CHANNEL FORMATION FOR SEMICONDUCTOR DEVICE - Methods and structures for forming semiconductor channels based on gate fringing effect are disclosed. In one embodiment, a NAND flash memory device comprises multiple NAND strings of memory transistors. Each memory transistor includes a charge trapping layer and a gate electrode formed on the charge trapping layer. The memory transistors are formed close to each other to form a channel between an adjacent pair of the memory transistors based on a gate fringing effect associated with the adjacent pair of the memory transistors. | 08-12-2010 |
20100220533 | NON-DIFFUSION JUNCTION SPLIT-GATE NONVOLATILE MEMORY CELLS AND ARRAYS, METHODS OF PROGRAMMING, ERASING, AND READING THEREOF, AND METHODS OF MANUFACTURE - Nonvolatile flash memory systems and methods are disclosed having a semiconductor substrate of a first conductivity type, including non-diffused channel regions through which electron flow is induced by application of voltage to associated gate elements. A plurality of floating gates are spaced apart from one another and each insulated from the channel region. A plurality of control gates are spaced apart from one another and insulated from the channel region, with each control gate being located between a first floating gate and a second floating gate and capacitively coupled thereto to form a subcell. A plurality of spaced-apart assist gates are insulated from the channel region, with each assist gate being located between and insulated from adjacent subcells. The channel is formed of three regions, two beneath adjacent control gate elements as well as a third region between the first two and beneath an associated assist gate. | 09-02-2010 |
20100238731 | PARTIAL LOCAL SELF-BOOSTING OF A MEMORY CELL CHANNEL - A method for partial local self-boosting of a memory cell channel is disclosed. As a part of memory cell channel partial local self-boosting, an isolating memory cell located on a source side of a program inhibited memory cell is turned off and a gating memory cell located on a drain side of the program inhibited memory cell is used to pass a pre-charge voltage to the program inhibited memory cell to provide a pre-charge voltage to a channel of the program inhibited memory cell. Moreover, a pre-charge voltage is passed to a buffering memory cell located on the source side of the program inhibited memory cell to provide a pre-charge voltage to a channel of the buffering memory cell and the gating memory cell that is located on the drain side of the program inhibited memory cell is turned off. During programming, a program voltage is applied to the gate of the program inhibited memory cell where a channel voltage of the program inhibited memory cell is raised above a level raised by the pre-charge voltage. | 09-23-2010 |
20110286276 | PARTIAL LOCAL SELF BOOSTING FOR NAND - A memory system is programmed with minimal program disturb and reduced junction and channel leakage during self-boosting. Pre-charging bias signals are applied to word lines adjacent to a selected word line before a program signal is applied to the selected word line and a pass signal is applied to the remaining word lines. The pre-charging bias signals apply a pre-charge to the memory cells. The pre-charging bias signals are chosen to improve the isolation of the memory cells on word lines adjacent to the selected word line, improve self boost efficiency and reduce current leakage to prevent or reduce program disturb and/or programming errors especially in the inhibited memory cells on the selected word line. | 11-24-2011 |
20140104957 | PARTIAL LOCAL SELF BOOSTING FOR NAND - A memory system is programmed with minimal program disturb and reduced junction and channel leakage during self-boosting. Pre-charging bias signals are applied to word lines adjacent to a selected word line before a program signal is applied to the selected word line and a pass signal is applied to the remaining word lines. The pre-charging bias signals apply a pre-charge to the memory cells. The pre-charging bias signals are chosen to improve the isolation of the memory cells on word lines adjacent to the selected word line, improve self boost efficiency and reduce current leakage to prevent or reduce program disturb and/or programming errors especially in the inhibited memory cells on the selected word line. | 04-17-2014 |
20140159138 | GATE FRINGINE EFFECT BASED CHANNEL FORMATION FOR SEMICONDUCTOR DEVICE - Methods and structures for forming semiconductor channels based on gate fringing effect are disclosed. In one embodiment, a NAND flash memory device comprises multiple NAND strings of memory transistors. Each memory transistor includes a charge trapping layer and a gate electrode formed on the charge trapping layer. The memory transistors are formed close to each other to form a channel between an adjacent pair of the memory transistors based on a gate fringing effect associated with the adjacent pair of the memory transistors. | 06-12-2014 |