Patent application number | Description | Published |
20140131881 | INTEGRATED CIRCUITS AND METHODS OF FORMING INTEGRATED CIRCUITS WITH INTERLAYER DIELECTRIC PROTECTION - Integrated circuits and methods of forming integrated circuits are provided herein. In an embodiment, a method of forming an integrated circuit includes providing a base substrate having an embedded electrical contact disposed therein. An interlayer dielectric is formed overlying the base substrate, and a recess is etched through the interlayer dielectric over the embedded electrical contact. A protecting liner is formed in the recess and over an exposed surface of the embedded electrical contact in the recess. The protecting liner includes at least two liner layers that have materially different etch rates in different etchants. A portion of the protecting liner is removed over the surface of the embedded electrical contact to again expose the surface of the embedded electrical contact in the recess. An embedded electrical interconnect is formed in the recess. The embedded electrical interconnect overlies the protecting liner on sides of the recess. | 05-15-2014 |
20140327139 | CONTACT LINER AND METHODS OF FABRICATION THEREOF - Contact structures and methods of fabricating contact structures of semiconductor devices are provided. One method includes, for instance: obtaining a substrate including a dielectric layer over the substrate; patterning the dielectric layer with at least one contact opening; providing a contact liner within the at least one contact opening in the dielectric layer; and filling the contact liner with a conductive material. In enhanced aspects, providing the contact liner within the at least one contact opening includes: depositing a first layer within the at least one contact opening in the dielectric layer; depositing a second layer over the first layer within the at least one contact opening; depositing at least one intermediate layer over the second layer within the at least one contact opening; and depositing a top layer over the at least one intermediate layer within the at least one contact opening. | 11-06-2014 |
20150311083 | REPLACEMENT LOW-K SPACER - A method includes providing a gate structure having a dummy gate, a first spacer along a side of the gate. The dummy gate and the spacer are removed to expose a gate dielectric. A second spacer is deposited on at least one side of a gate structure cavity and a top of the gate dielectric. A bottom portion of the second spacer is removed to expose the gate dielectric and the gate structure is wet cleaned. | 10-29-2015 |
20150318217 | MIXED N/P TYPE NON-PLANAR SEMICONDUCTOR STRUCTURE WITH MULTIPLE EPITAXIAL HEADS AND METHOD OF MAKING SAME - A non-planar semiconductor structure includes mixed n-and-p type raised semiconductor structures, e.g., fins, having epitaxial structures grown on top surfaces thereof, for example, epitaxial silicon and silicon germanium, naturally growing into a diamond shape. The surface area of the epitaxial structures is increased by removing portion(s) thereof, masking each type as the other type is grown and then subsequently modified by the removal. The removal may create multi-head (e.g., dual-head) epitaxial structures, together with the neck of the respective raised structure resembling a Y-shape. | 11-05-2015 |
20150318351 | MULTIPLE EPITAXIAL HEAD RAISED SEMICONDUCTOR STRUCTURE AND METHOD OF MAKING SAME - A non-planar semiconductor structure includes raised semiconductor structures, e.g., fins, having epitaxial structures grown on top surfaces thereof, for example, epitaxial silicon naturally growing into a diamond shape. The surface area of the epitaxial structure may be increased by removing portion(s) thereof. The removal may create a multi-head (e.g., dual-head) epitaxial structure, together with the neck of the raised structure resembling a Y-shape. Raised structures that are not intended to include an epitaxial structure will be masked during epitaxial structure creation and modification. In addition, in order to have a uniform height, the filler material surrounding the raised structures is recessed around those to receive epitaxial structures. | 11-05-2015 |
20150332963 | T-SHAPED CONTACTS FOR SEMICONDUCTOR DEVICE - A transistor, planar or non-planar (e.g., FinFET), includes T-shaped contacts to the source, drain and gate. The top portion of the T-shaped contact is wider than the bottom portion, the bottom portion complying with design rule limits. A conductor-material filled trench through a multi-layer etching stack above the transistor provides the top portions of the T-shaped contacts. Tapered spacers along inner sidewalls of the top contact portion prior to filling allow for etching a narrower bottom trench down to the gate, and to the source/drain for silicidation prior to filling. | 11-19-2015 |
20150333121 | SHALLOW TRENCH ISOLATION INTEGRATION METHODS AND DEVICES FORMED THEREBY - Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion. | 11-19-2015 |
20150380409 | THRESHOLD VOLTAGE CONTROL FOR MIXED-TYPE NON-PLANAR SEMICONDUCTOR DEVICES - A range of lowest, low and regular threshold voltages are provided to three p-type devices and three n-type devices co-fabricated on a same substrate. For the p-type devices, the range is achieved for the lowest using an additional thick layer of a p-type work function metal in a gate structure and oxidizing it, the low Vt is achieved with the thick p-type work function metal alone, and the regular Vt is achieved with a thinner layer of the p-type work function metal. For the n-type devices, the lowest Vt is achieved by implanting tantalum nitride with arsenic, argon, silicon or germanium and not adding any of the additional p-type work function metal in the gate structure, the low Vt is achieved by not adding the additional p-type work function metal, and the regular Vt is achieved with a thinnest layer of the p-type work function metal. | 12-31-2015 |
20160049400 | THRESHOLD VOLTAGE CONTROL FOR MIXED-TYPE NON-PLANAR SEMICONDUCTOR DEVICES - A range of lowest, low and regular threshold voltages are provided to three p-type devices and three n-type devices co-fabricated on a same substrate. For the p-type devices, the range is achieved for the lowest using an additional thick layer of a p-type work function metal in a gate structure and oxidizing it, the low Vt is achieved with the thick p-type work function metal alone, and the regular Vt is achieved with a thinner layer of the p-type work function metal. For the n-type devices, the lowest Vt is achieved by implanting tantalum nitride with arsenic, argon, silicon or germanium and not adding any of the additional p-type work function metal in the gate structure, the low Vt is achieved by not adding the additional p-type work function metal, and the regular Vt is achieved with a thinnest layer of the p-type work function metal. | 02-18-2016 |
20160049468 | PRODUCT COMPRISED OF FINFET DEVICES WITH SINGLE DIFFUSION BREAK ISOLATION STRUCTURES - An integrated circuit product is disclosed that includes a plurality of trenches in a semiconducting substrate that define first, second and third fins, wherein the fins are side-by-side, and wherein the second fin is positioned between the first and third fins, a layer of insulating material in the plurality of trenches such that a desired height of the first, second and third fins is positioned above an upper surface of the layer of insulating material, a recess defined in the second fin that at least partially defines a cavity in the layer of insulating material, an SDB isolation structure in the cavity on the recessed portion of the second fin, wherein the SDB isolation structure has an upper surface that is above the upper surface of the layer of insulating material, and a gate structure for a transistor positioned above the SDB isolation structure. | 02-18-2016 |
20160126336 | METHOD OF IMPROVED CA/CB CONTACT AND DEVICE THEREOF - Processes for forming merged CA/CB constructs and the resulting devices are disclosed. Embodiments include providing a replacement metal gate (RMG) between first and second sidewall spacers surrounded by an insulator on a substrate, the RMG having a dielectric layer directly on the first and second sidewall spacers and having metal on the dielectric layer; providing an oxide layer over the insulator, the first and second sidewall spacers, and the RMG; forming a source/drain contact hole through the oxide layer and the insulator, adjacent to the first sidewall spacer; forming a gate contact hole through the oxide layer over the source/drain contact hole and extending to the metal of the RMG; enlarging the source/drain contact hole to the metal of the RMG; and filling the enlarged source/drain contact hole and gate contact hole with metal. | 05-05-2016 |
Patent application number | Description | Published |
20140318230 | STIRRER CELL MODULE AND METHOD OF USING - Baffles useful for stirrer cell modules, stirrer cell modules including the baffles, and methods of using the baffles and modules, are disclosed. | 10-30-2014 |
20150375177 | CROSSLINKED CELLULOSIC MEMBRANES - Disclosed are crosslinked porous membranes comprising a cellulosic material and an aromatic hydrophobic moiety or a copolymer of the formula A-B-A (I) or A-B (II), wherein block A, for example, polyglycerol, a polymer of allylglycidyl ether, or a copolymer of glycidol and allyl glycidyl ether, or a polymer of allyl glycidyl ether or a copolymer of glycidol and allyl glycidyl ether wherein one or more allyl groups having been replaced by hydrophilic groups. Block B is an aromatic hydrophobic moiety. An example of the aromatic hydrophobic moiety is polyethersulfone. Also disclosed is a method for preparing such membranes. | 12-31-2015 |
20150376362 | MEMBRANES COMPRISING CELLULOSIC MATERIAL AND HYDROPHILIC BLOCK COPOLYMER (V) - Disclosed is a porous membrane comprising a cellulosic material and a copolymer of the formula: A-B-A (I) or A-B (II), wherein block A, for example, polyglycerol, a polymer of allyl glycidyl ether, or a copolymer of glycidol and allyl glycidyl ether, or a polymer of allyl glycidyl ether or a copolymer of glycidol and allyl glycidyl ether wherein one or more allyl groups having been replaced by hydrophilic groups. Also disclosed is a method for preparing such a membrane. | 12-31-2015 |
Patent application number | Description | Published |
20080270762 | Method, System and Computer Program Product for Register Management in a Simulation Enviroment - A method for register management in a simulation environment including receiving an instruction from an instruction unit decode pipeline. An address generation interlock (AGI) function is executed in the simulation environment if the instruction is an AGI instruction. The executing an AGI function is responsive to a pool of registers controlled by a register manager and to the instruction. An early AGI function is executed in the simulation environment if the instruction is an early AGI instruction. The executing an early AGI function is responsive to the pool of registers and to the instruction. | 10-30-2008 |
20090198964 | METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR OUT OF ORDER INSTRUCTION ADDRESS STRIDE PREFETCH PERFORMANCE VERIFICATION - A method, system, and computer program product are provided for verifying out of order instruction address (IA) stride prefetch performance in a processor design having more than one level of cache hierarchies. Multiple instruction streams are generated and the instructions loop back to corresponding instruction addresses. The multiple instruction streams are dispatched to a processor and simulation application to process. When a particular instruction is being dispatched, the particular instruction's instruction address and operand address are recorded in the queue. The processor is monitored to determine if the processor executes fetch and prefetch commands in accordance with the simulation application. It is checked to determine if prefetch commands are issued for instructions having three or more strides. | 08-06-2009 |
20090210681 | Method and Apparatus of Handling Instruction Rejects, Partial Rejects, Stalls and Branch Wrong in a Simulation Model - A method and apparatus of handling instruction rejects, partial rejects, stalls and branch wrong in a simulation model provides pipeline states for various unit verification. It defines an instruction train to encounter many events of the hardware verifications. Drivers and monitors at a unit and a core simulation level can hook into the pipeline states and perform the verification easily without having to restructure the instructions in the pipeline due to rejects, partial rejects, stalls, branch wrongs. Different event counters have been placed in the instruction pipe during the events and expand the instruction train such that the instruction train provides an accurate and detailed state of each instruction so the hardware logic signals and data can be tracked and identified from each state. | 08-20-2009 |
Patent application number | Description | Published |
20140153174 | COMPUTER SYSTEM - A computer system includes a desk, and a first display and a first keyboard arranged on a desk panel of the desk and flexibly connected to the desk panel. The panel board includes at least two layers; an edge of a top layer of the panel board is flexibly connected to a second layer of the panel board; a lower surface of the top layer of the panel board is used as a second display and an upper surface of a second layer of the panel board is used as a second keyboard; and the first display, the first key board, the second display, and the second keyboard are all connected to the computer. The computer system of the present disclosure effectively protects eye sights, reduces the probability of shortsightedness, greatly increases the amount of exercise, consumes unnecessary energy, reduces the storage of energy and production of fat, further results in loss of weight, and at the same time strengthens physical exercise and improves health states. | 06-05-2014 |
20140278344 | ENGLISH TRAINING METHOD AND DEVICE - The present disclosure provides an English training method, including the following steps: classifying and storing words according to predetermined word classification rules; receiving a user command for extracting a corresponding word according to a classification of the word, and extracting the corresponding word according to the user command and outputting the word in audio or video form; the word classification rules including: combining two consonants with five vowels a, e, i, o, and u respectively to form words; or using a main word or a transformation of the main word as a main body, and combining the main body with 26 letters of the English alphabet in sequence to form words; or combining the five vowels a, e, i, o, and u with other letters of the English alphabet to form word roots, and combining each of the word roots with the 26 letters of the English alphabet in sequence to form words; or matching a whole English sentence or a whole English paragraph with a Chinese song; or noting a pronunciation of the word in the English sentence by Chinese. | 09-18-2014 |