Patent application number | Description | Published |
20100109725 | DLL CIRCUIT HAVING DUTY CYCLE CORRECTION AND METHOD OF CONTROLLING THE SAME - A delay locked loop (DLL) circuit includes a duty cycle correcting unit configured to correct a duty cycle of a reference clock signal in response to a duty cycle correction signal and generate a correction clock signal. A feedback loop of the DLL circuit performs a delay lock operation on the correction clock signal and generates an output clock signal. A first duty cycle detecting unit detects a duty cycle of the correction clock signal and generates a first detection signal and a second duty cycle detecting unit detects a duty cycle of the output clock signal and generates a second detection signal. Finally, a duty cycle control unit generates the duty cycle correction signal in response to the first detection signal and the second detection signal to perform the duty cycle correction. | 05-06-2010 |
20100156486 | DLL CIRCUIT HAVING ACTIVATION POINTS - A delay locked loop (DLL) circuit includes a delay line configured to generate a delay clock signal by delaying a reference clock signal in response to a delay control signal, the delay line having two or more initial activation points, wherein the initial activation points are selected according to an initial value of the delay control signal; a delay compensating unit configured to generate a feedback clock signal by delaying the delay clock signal for a predetermined time; a phase detecting unit configured to generate a phase detection signal by comparing a phase of the reference clock signal to a phase of the feedback clock signal; and a delay control unit configured to generate the delay control signal in response to the phase detection signal. | 06-24-2010 |
20100264966 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF CONTROLLING THE SAME - A semiconductor integrated circuit includes an update control unit configured to generate an update control signal in response to a first command and a second command; and a DLL (Delay Locked Loop) circuit configured to generate an output clock by controlling a phase of an external clock in response to the update control signal. | 10-21-2010 |
20100301911 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus having a clock signal generation circuit and a data output circuit is presented. The apparatus includes a delay locked loop (DLL), a phase locked loop (PLL), a frequency discrimination unit, and a data output buffer. The DLL circuit is configured to negatively delay a clock signal to generate a DLL clock signal. The PLL circuit is configured to receive the DLL clock signal to generate a control voltage in response to a frequency of the DLL clock signal and to generate a PLL clock signal of a frequency corresponding to a level of the control voltage. The frequency discrimination unit is configured to discriminate a frequency of the DLL clock signal in accordance with the level of the control voltage to generate a frequency discrimination signal. The data output buffer is configured to receive the DLL clock signal or the PLL clock signal to buffer output data signals. | 12-02-2010 |
20100308884 | CLOCK RECEIVER IN SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF CONTROLLING THE SAME - A clock receiver in a semiconductor integrated circuit includes a first clock buffer configured to buffer an external clock to generate a low frequency buffered clock in response to a first operation signal; a second clock buffer configured to buffer the external clock to generate a high frequency buffered clock in response to a second operation signal; and an internal clock generating unit configured to receive the low frequency buffered clock and the high frequency buffered clock, to control states of the first operation signal and the second operation signal and to generate an internal clock. | 12-09-2010 |
20110025390 | UPDATE CONTROL APPARATUS IN DLL CIRCUIT - An update control apparatus in a DLL circuit is provided. The update control apparatus includes a logic value determination, a phase information collection unit, and an update control unit. The logic value determination unit is configured to determine a logic value of a phase detection signal for a first period interval of a reference clock signal to generate a phase information signal, and configured to extend the first period interval into a second period interval when an extension instruction signal is enabled. The phase information collection unit is configured to determine consecutive logic values of an update possible signal to generate the extension instruction signal, and configured to collect the phase information signal to generate an update information signal. The update control unit is configured to generate the update possible signal, a valid interval signal, and an update control signal in response to the update information signal. | 02-03-2011 |
20110102035 | SEMICONDUCTOR INTEGRATED CIRCUIT HAVING DELAY LOCKED LOOP CIRCUIT - A semiconductor integrated circuit is provided. The semiconductor integrated circuit includes: a delay locked loop (DLL) output block configured to delay an input clock signal by a predetermined time in response to a plurality of delay control signals and provide a DLL clock signal; a locking control block configured to compare a phase of a reference clock signal and a phase of a feedback clock signal, and synchronize the phase of the reference clock signal and the phase of the feedback clock signal in response to the plurality of delay control signals; and a locking detection block configured to detect whether the phase of the reference clock signal and the phase of the feedback clock signal are synchronized and the DLL clock signal is locked, wherein, when the DLL clock signal is locked, the locking control block provides the reference clock signal, which is obtained by dividing the input clock signal by n (where n is a natural number equal to or greater than 2), as an internal DLL clock signal. | 05-05-2011 |
20110204951 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus for generating an internal voltage includes a control code output block and an internal voltage generation block. The control code output block is configured to output a variable code having a code value corresponding to a voltage level of an internal voltage. The internal voltage generation block is configured to compare the variable code to a setting code and controls the voltage level of the internal voltage according to the comparison. | 08-25-2011 |
20120007646 | DLL CIRCUIT HAVING ACTIVATION POINTS - A delay locked loop (DLL) circuit includes a delay line configured to generate a delay clock signal by delaying a reference clock signal in response to a delay control signal, the delay line having two or more initial activation points, wherein the initial activation points are selected according to an initial value of the delay control signal; a delay compensating unit configured to generate a feedback clock signal by delaying the delay clock signal for a predetermined time; a phase detecting unit configured to generate a phase detection signal by comparing a phase of the reference clock signal to a phase of the feedback clock signal; and a delay control unit configured to generate the delay control signal in response to the phase detection signal. | 01-12-2012 |