Patent application number | Description | Published |
20090129169 | METHOD AND APPARATUS FOR READING DATA FROM FLASH MEMORY - Methods and apparatus are disclosed, such as those involving a flash memory device that includes an array of memory cells. One such method includes detecting values of charges stored in selected memory cells in the memory cell array. The method also includes processing the detected values in accordance with a Viterbi algorithm so as to determine data stored in the selected memory cells. In one embodiment, the flash memory cell array includes word lines and bit lines. Detecting the values of charges includes detecting values of charges stored in a selected row of memory cells by selecting one of the word lines. The Viterbi algorithm provides correct data where inter-signal interference between the cells affects the accuracy of read data. For example, the Viterbi algorithm can be used to supplement error correction codes (ECC). | 05-21-2009 |
20120242670 | MEMORY SYSTEM AND METHOD FOR IMPROVED UTILIZATION OF READ AND WRITE BANDWIDTH OF A GRAPHICS PROCESSING SYSTEM - A system for processing graphics data. The graphics processing system includes an embedded memory array having at least three separate banks of single-ported memory in which graphics data are stored. A memory controller coupled to the banks of memory writes post-processed data to a first bank of memory while reading data from a second bank of memory. A synchronous graphics processing pipeline processes the data read from the second bank of memory and provides the post-processed graphics data to the memory controller to be written back to a bank of memory. The processing pipeline concurrently processes an amount of graphics data at least equal to that included in a page of memory. A third bank of memory is precharged concurrently with writing data to the first bank and reading data from the second bank in preparation for access when reading data from the second bank of memory is completed. | 09-27-2012 |
20130073807 | HYBRID MEMORY MANAGEMENT - Methods and apparatus for managing data storage in hybrid memory devices utilizing single level and multi-level memory cells. Logical addresses can be distributed between single level and multilevel memory cells based on a frequency of write operations performed. Initial storage of data corresponding to a logical address in memory can be determined by various methods including initially writing all data to single level memory or initially writing all data to multilevel memory. Other methods permit a host to direct logical address writes to single level or multilevel memory cells based on anticipated usage. | 03-21-2013 |
20130286745 | METHOD AND APPARATUS FOR READING DATA FROM NON-VOLATILE MEMORY - Methods and apparatus are disclosed, such as those involving a flash memory device that includes an array of memory cells. One such method includes detecting values of charges stored in selected memory cells in the memory cell array. The method also includes processing the detected values in accordance with a Viterbi algorithm so as to determine data stored in the selected memory cells. In one embodiment, the flash memory cell array includes word lines and bit lines. Detecting the values of charges includes detecting values of charges stored in a selected row of memory cells by selecting one of the word lines. The Viterbi algorithm provides correct data where inter-signal interference between the cells affects the accuracy of read data. For example, the Viterbi algorithm can be used to supplement error correction codes (ECC). | 10-31-2013 |
20140237326 | METHOD AND APPARATUS FOR READING DATA FROM NON-VOLATILE MEMORY - Methods and apparatus are disclosed, such as those involving a flash memory device that includes an array of memory cells. One such method includes detecting values of charges stored in selected memory cells in the memory cell array. The method also includes processing the detected values in accordance with a Viterbi algorithm so as to determine data stored in the selected memory cells. In one embodiment, the flash memory cell array includes word lines and bit lines. Detecting the values of charges includes detecting values of charges stored in a selected row of memory cells by selecting one of the word lines. The Viterbi algorithm provides correct data where inter-signal interference between the cells affects the accuracy of read data. For example, the Viterbi algorithm can be used to supplement error correction codes (ECC). | 08-21-2014 |
20140268536 | HIGH DENSITY SERVER STORAGE UNIT - A rack mountable 1U storage unit includes a plurality of memory modules arranged in two groups. The storage unit also has control circuitry. The memory modules have a dedicated exhaust channel to draw heat away from the memory modules. The exhaust channel for the memory modules is disposed over and is physically separated from the exhaust channel for the control circuitry. The storage unit can accommodate up to 42 memory modules due to a unique method of placing the individual memory modules. | 09-18-2014 |
20140281177 | HYBRID MEMORY MANAGEMENT - Methods and apparatus for managing data storage in hybrid memory devices utilizing single level and multi-level memory cells. Logical addresses can be distributed between single level and multilevel memory cells based on a frequency of write operations performed. Initial storage of data corresponding to a logical address in memory can be determined by various methods including initially writing all data to single level memory or initially writing all data to multilevel memory. Other methods permit a host to direct logical address writes to single level or multilevel memory cells based on anticipated usage. | 09-18-2014 |
20150077922 | HIGH CAPACITY STORAGE UNIT - A rack mountable 10U storage unit includes a plurality of memory modules arranged in multiple rows. The storage unit also has control circuitry. Each of the memory modules have multiple heating zones and a heat spreader coupled to it. The memory modules may have heat spreaders having differing thermal dissipation capacity coupled to them. The storage unit can accommodate up to 120 memory modules due to a unique method of placing the individual memory modules. | 03-19-2015 |