Patent application number | Description | Published |
20080276011 | STRUCTURE FOR OPTION ROM CHARACTERIZATION - A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is disclosed for option ROM characterization by establishing an isolating execution environment for an expansion adapter of a computer, the adapter having an option ROM containing initialization code for the adapter, executing the initialization code for the expansion adapter in the isolating execution environment, identifying operating characteristics of the option ROM, including characteristics of the option ROM unavailable prior to execution of the initialization code in the isolating execution environment, and allocating virtual memory address space in a normal execution environment of the computer to the option ROM of the expansion adapter in dependence upon the identified operating characteristics of the option ROM. | 11-06-2008 |
20120297232 | ADJUSTING THE CLOCK FREQUENCY OF A PROCESSING UNIT IN REAL-TIME BASED ON A FREQUENCY SENSITIVITY VALUE - A system, method, and medium for adjusting an input clock frequency of a processor in real-time based on one or more hardware metrics. First, the processor is characterized for a plurality of workloads. Next, the frequency sensitivity value of the processor for each of the workloads is calculated. Hardware metrics are also monitored and the values of these metrics are stored for each of the workloads. Then, linear or polynomial regression is performed to match the metrics to the frequency sensitivity of the processor. The linear or polynomial regression will produce a formula and coefficients, and the coefficients are applied to the metrics in real-time to calculate a frequency sensitivity value of an application executing on the processor. Then, the frequency sensitivity value is utilized to determine whether to adjust the input clock frequency of the processor. | 11-22-2012 |
20130262780 | Apparatus and Method for Fast Cache Shutdown - An apparatus and method to enable a fast cache shutdown is disclosed. In one embodiment, a cache subsystem includes a cache memory and a cache controller coupled to the cache memory. The cache controller is configured to, upon restoring power to the cache subsystem, inhibit writing of modified data exclusively into the cache memory. | 10-03-2013 |
20130283078 | DYNAMIC PERFORMANCE CONTROL OF PROCESSING NODES - An apparatus and method for performance control of processing nodes is disclosed. In one embodiment, a system includes a processing node and a power management unit configured to, for each of a plurality of time intervals, monitor an activity level of the processing node, cause the processing node to operate at a high operating point during one successive time interval if the activity level in the given interval is greater than a high activity threshold, operate at a low operating point at least one successive time interval if the activity level is less than a low activity threshold, or enable operating system software to cause the processing node to operate at one of one or more predefined intermediate operating points of the plurality of operating points if the activity level is less than the high activity threshold and greater than the low activity threshold. | 10-24-2013 |
20140143565 | Setting Power-State Limits based on Performance Coupling and Thermal Coupling between Entities in a Computing Device - The described embodiments include a computing device with a first entity and a second entity. In the computing device, a management controller dynamically sets a power-state limit for the first entity based on a performance coupling and a thermal coupling between the first entity and the second entity. | 05-22-2014 |
20140149772 | Using a Linear Prediction to Configure an Idle State of an Entity in a Computing Device - The described embodiments include a computing device with one or more entities (processor cores, processors, etc.). In some embodiments, during operation, a thermal power management unit in the computing device uses a linear prediction to compute a predicted duration of a next idle period for an entity based on the duration of one or more previous idle periods for the entity. Based on the predicted duration of the next idle period, the thermal power management unit configures the entity to operate in a corresponding idle state. | 05-29-2014 |
20140173298 | PERFORMANCE AWARE IDLE POWER MANAGEMENT - Methods, systems, and media are provided for power management. The power management includes, but is not limited to storing at a computer system a history of canceled entries into a low power state that interrupted a transition of the unit from an active mode to the low power state and disallowing transition of the unit into the low power state when a number of canceled entries indicated by the history of canceled entries exceeds a canceled entry threshold. | 06-19-2014 |
20140181553 | Idle Phase Prediction For Integrated Circuits - A method and apparatus for idle phase prediction in integrated circuits is disclosed. In one embodiment, an integrated circuit (IC) includes a functional unit configured to cycle between intervals of an active state and an idle state. The IC further includes a prediction unit configured to record a history of idle state durations for a plurality of intervals of the idle state. Based on the history of idle state durations, the prediction unit is configured to generate a prediction of the duration of the next interval of the idle state. The prediction may be used by a power management unit to, among other uses, determine whether to place the functional unit in a low power (e.g., sleep) state. | 06-26-2014 |
20140181556 | Idle Phase Exit Prediction - A method and apparatus for exiting a low power state based on a prior prediction is disclosed. An integrated circuit (IC) includes a functional unit configured to, during operation, cycle between intervals of an active state and intervals of an idle state. The IC also include a power management unit configured to place the functional unit in a low power state responsive to the functional unit entering the idle state. The power management unit is further configured to preemptively cause the functional unit to exit the low power state at a predetermined time after entering the low power. The predetermined time is based on a prediction of idle state duration made prior to entering the low power state. The prediction may be generated by a prediction unit, based on a history of durations of intervals in which the functional unit was in the idle state. | 06-26-2014 |
20140281592 | Global Efficient Application Power Management - A method, system and computer-readable medium for allocating power among computing resources are provided. The method calculates an activity level of a first computer resource. When the activity level is less than a threshold value, the method increases the power allocation to a second computing resource. When the activity level exceeds the threshold value, the method decreases the power allocation to the second computing resource. | 09-18-2014 |
20140362518 | THERMAL MANAGEMENT OF A PORTABLE COMPUTING DEVICE - Various computing devices and methods of thermally managing the same are disclosed. In one aspect, an apparatus is provided that includes a case and a first sensor in the case. a case and a first sensor in the case. The first sensor is operable to generate an output in response to sensing contact with a body part of a user. The computing device manages thermal behavior of the computing device responsive to the output. | 12-11-2014 |