Patent application number | Description | Published |
20090065898 | INTEGRATED BEOL THIN FILM RESISTOR - In the course of forming a resistor in the back end of an integrated circuit, an intermediate dielectric layer is deposited and a trench etched through it and into a lower dielectric layer by a controllable amount, so that the top of a resistor layer deposited in the trench is close in height to the top of the lower dielectric layer; the trench is filled and the resistor layer outside the trench is removed, after which a second dielectric layer is deposited. Vias passing through the second dielectric layer to contact the resistor then have the same depth as vias contacting metal interconnects in the lower dielectric layer. A tri-layer resistor structure is employed in which the resistive film is sandwiched between two protective layers that block diffusion between the resistor and BEOL ILD layers. | 03-12-2009 |
20090270017 | Slurryless Mechanical Planarization for Substrate Reclamation - A patterned portion of a patterned semiconductor substrate is removed by abrasive mechanical planarization employing an abrasive pad but without employing any slurry. Preferably, water is supplied to enhance the removal rate during the mechanical planarization. The removal rate of material is substantially independent for common materials employed in back-end-of-line (BEOL) semiconductor materials, which enables non-selective removal of the material containing metallization structures. The removal rate of silicon is lower than the removal rate for the BEOL semiconductor materials, enabling a self-stopping planarization process. | 10-29-2009 |
20100127395 | METHODS FOR SELECTIVE REVERSE MASK PLANARIZATION AND INTERCONNECT STRUCTURES FORMED THEREBY - Methods for planarizing layers of a material, such as a dielectric, and interconnect structures formed by the planarization methods. The method includes depositing a first dielectric layer on a top surface of multiple conductive features and on a top surface of a substrate between the conductive features. A portion of the first dielectric layer is selectively removed from the top surface of at least one of the conductive features without removing a portion the first dielectric layer that is between the conductive features. A second dielectric layer is formed on the top surface of the at least one of the conductive features and on a top surface of the first dielectric layer, and a top surface of the second dielectric layer is planarized. A layer operating as an etch stop is located between the top surface of at least one of the conductive features and the second dielectric layer. | 05-27-2010 |
20100248479 | CMP METHOD - The instant invention is a method of polishing a substrate including contacting a substrate having at least one metal layer including copper with a chemical-mechanical polishing composition. The CMP composition includes an abrasive, a surfactant, an oxidizer, an organic acid including polyacrylic acid or polymethacrylic acid, a corrosion inhibitor, and a liquid carrier. A portion of the copper in the metal layer is abraded to polish the substrate. A second CMP composition contacts the abraded substrate, the second acrylate free composition including an abrasive, a surfactant, an oxidizer, and a corrosion inhibitor, and a liquid carrier. Any dendrites that may have formed on the substrate are removed through abrasion. | 09-30-2010 |
20100327219 | SOLUTION FOR FORMING POLISHING SLURRY, POLISHING SLURRY AND RELATED METHODS - A solution for forming a polishing slurry, the polishing slurry and related methods are disclosed. The solution for forming a polishing slurry may include 1H-benzotriazole (BTA) dissolved in an ionic surfactant such as a sodium alkyl sulfate solution, and perhaps a polyacrylic acid (PAA) solution. The solution can be filtered and used in a polishing slurry. This approach to solubilizing BTA results in a high BTA concentration in a polishing slurry without addition of foreign components to the slurry or increased safety hazard. In addition, the solution is easier to ship because it is very stable (e.g., can be frozen and thawed) and has less volume compared to conventional approaches. Further, the polishing slurry performance is vastly improved due to the removal of particles that can cause scratching. | 12-30-2010 |
20110127635 | Integrated BEOL Thin Film Resistor - In the course of forming a resistor in the back end of an integrated circuit, an intermediate dielectric layer is deposited and a trench etched through it and into a lower dielectric layer by a controllable amount, so that the top of a resistor layer deposited in the trench is close in height to the top of the lower dielectric layer; the trench is filled and the resistor layer outside the trench is removed, after which a second dielectric layer is deposited. Vias passing through the second dielectric layer to contact the resistor then have the same depth as vias contacting metal interconnects in the lower dielectric layer. A tri-layer resistor structure is employed in which the resistive film is sandwiched between two protective layers that block diffusion between the resistor and BEOL ILD layers. | 06-02-2011 |
20110315527 | PLANAR CAVITY MEMS AND RELATED STRUCTURES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES - Planar cavity Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structure are provided. The method includes forming at least one Micro-Electro-Mechanical System (MEMS) cavity having a planar surface using a reverse damascene process. | 12-29-2011 |
20110316097 | PLANAR CAVITY MEMS AND RELATED STRUCTURES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES - A method of forming at least one Micro-Electro-Mechanical System (MEMS) cavity includes forming a first sacrificial cavity layer over a wiring layer and substrate. The method further includes forming an insulator layer over the first sacrificial cavity layer. The method further includes performing a reverse damascene etchback process on the insulator layer. The method further includes planarizing the insulator layer and the first sacrificial cavity layer. The method further includes venting or stripping of the first sacrificial cavity layer to a planar surface for a first cavity of the MEMS. | 12-29-2011 |
20120070979 | METHOD OF ELECTROLYTIC PLATING AND SEMICONDUCTOR DEVICE FABRICATION - The disclosure relates generally to semiconductor device fabrication, and more particularly to methods of electroplating used in semiconductor device fabrication. A method of electroplating includes: immersing an in-process substrate into an electrolytic plating solution to form a first metal layer on the in-process substrate; then performing a first chemical-mechanical polish to a liner on the in-process substrate followed by immersing the in-process substrate into the electrolytic plating solution to form a second metal layer on the first metal layer and the liner; and performing a second chemical-mechanical polish to the liner. | 03-22-2012 |
20120086101 | INTEGRATED CIRCUIT AND INTERCONNECT, AND METHOD OF FABRICATING SAME - The disclosure relates generally to integrated circuits (IC), IC interconnects, and methods of fabricating the same, and more particularly, high performance inductors. The IC includes at least one trench within a dielectric layer disposed on a substrate. The trench is conformally coated with a liner and seed layer, and includes an interconnect within. The interconnect includes a hard mask on the sidewalls of the interconnect. | 04-12-2012 |
20130062603 | TEST STRUCTURE AND CALIBRATION METHOD - A test structure for measuring a Micro-Electro-Mechanical System (MEMS) cavity height structure and calibration method. The method includes forming a sacrificial cavity material over a plurality of electrodes and forming an opening into the sacrificial cavity material. The method further includes forming a transparent or substantially transparent material in the opening to form a transparent or substantially transparent window. The method further includes tuning a thickness of the sacrificial cavity material based on measurements obtained through the transparent or substantially transparent window. | 03-14-2013 |
20130078811 | SLURRY FOR CHEMICAL-MECHANICAL POLISHING OF METALS AND USE THEREOF - A composition and a method for chemical mechanical polishing. The composition includes a surfactant anion an alkyl alcohol and a diluent. The composition further includes abrasive particles and an oxidizer. The method includes providing the composition on a surface to be polished and polishing the surface by contacting the surface with a polishing pad. | 03-28-2013 |
20140131893 | METHODS FOR SELECTIVE REVERSE MASK PLANARIZATION AND INTERCONNECT STRUCTURES FORMED THEREBY - Methods for planarizing layers of a material, such as a dielectric, and interconnect structures formed by the planarization methods. The method includes depositing a first dielectric layer on a top surface of multiple conductive features and on a top surface of a substrate between the conductive features. A portion of the first dielectric layer is selectively removed from the top surface of at least one of the conductive features without removing a portion the first dielectric layer that is between the conductive features. A second dielectric layer is formed on the top surface of the at least one of the conductive features and on a top surface of the first dielectric layer, and a top surface of the second dielectric layer is planarized. A layer operating as an etch stop is located between the top surface of at least one of the conductive features and the second dielectric layer. | 05-15-2014 |
20140291802 | SEMICONDUCTOR STRUCTURES WITH METAL LINES - Disclosed are semiconductor structures with metal lines and methods of manufacture which reduce or eliminate extrusion formation. The method includes forming a metal wiring comprising a layered structure of metal materials with an upper constraining layer. The method further includes forming a film on the metal wiring which prevents metal extrusion during an annealing process. | 10-02-2014 |
20140308771 | MICRO-ELECTRO-MECHANICAL SYSTEM (MEMS) STRUCTURES AND DESIGN STRUCTURES - Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a Micro-Electro-Mechanical System (MEMS) beam structure by venting both tungsten material and silicon material above and below the MEMS beam to form an upper cavity above the MEMS beam and a lower cavity structure below the MEMS beam. | 10-16-2014 |
20150041932 | PLANAR CAVITY MEMS AND RELATED STRUCTURES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES - A method of forming at least one Micro-Electro-Mechanical System (MEMS) cavity includes forming a first sacrificial cavity layer over a wiring layer and substrate. The method further includes forming an insulator layer over the first sacrificial cavity layer. The method further includes performing a reverse damascene etchback process on the insulator layer. The method further includes planarizing the insulator layer and the first sacrificial cavity layer. The method further includes venting or stripping of the first sacrificial cavity layer to a planar surface for a first cavity of the MEMS. | 02-12-2015 |
20150137374 | COPPER WIRE AND DIELECTRIC WITH AIR GAPS - Approaches for fabricating copper wires in integrated circuits are provided. A method of manufacturing a semiconductor structure includes forming a wire opening in a mask. The method also includes electroplating a conductive material in the wire opening. The method additionally includes forming a cap layer on the conductive material. The method further includes removing the mask. The method still further includes forming spacers on sides of the conductive material. The method additionally includes forming a dielectric film on surfaces of the cap layer and the sidewall spacers. | 05-21-2015 |
20150137375 | COPPER WIRE AND DIELECTRIC WITH AIR GAPS - Approaches for fabricating copper wires in integrated circuits are provided. A method of manufacturing a semiconductor structure includes forming a wire opening in a mask. The method also includes electroplating a conductive material in the wire opening. The method additionally includes forming a cap layer on the conductive material. The method further includes removing the mask. The method still further includes forming spacers on sides of the conductive material. The method additionally includes forming a dielectric film on surfaces of the cap layer and the sidewall spacers. | 05-21-2015 |
20150140809 | INTEGRATED CIRCUIT AND INTERCONNECT, AND METHOD OF FABRICATING SAME - The disclosure relates generally to integrated circuits (IC), IC interconnects, and methods of fabricating the same, and more particularly, high performance inductors. The IC includes at least one trench within a dielectric layer disposed on a substrate. The trench is conformally coated with a liner and seed layer, and includes an interconnect within. The interconnect includes a hard mask on the sidewalls of the interconnect. | 05-21-2015 |
20150267084 | SLURRY FOR CHEMICAL-MECHANICAL POLISHING OF METALS AND USE THEREOF - A composition and a method for chemical mechanical polishing. The composition includes a surfactant anion an alkyl alcohol and a diluent. The composition further includes abrasive particles and an oxidizer. The method includes providing the composition on a surface to be polished and polishing the surface by contacting the surface with a polishing pad. | 09-24-2015 |
Patent application number | Description | Published |
20090087928 | COPPER CONTAMINATION DETECTION METHOD AND SYSTEM FOR MONITORING COPPER CONTAMINATION - A method of monitoring copper contamination. The method includes method, comprising: (a) ion-implanting an N-type dopant into a region of single-crystal silicon substrate, the region abutting a top surface of the substrate; (c) activating the N-type dopant by annealing the substrate at a temperature of 500° C. or higher in an inert atmosphere; (c) submerging, for a present duration of time, the substrate into an aqueous solution, the aqueous solution to be monitored for copper contamination; and (d) determining an amount of copper adsorbed from the aqueous solution by the region of the substrate. | 04-02-2009 |
20090088984 | COPPER CONTAMINATION DETECTION METHOD AND SYSTEM FOR MONITORING COPPER CONTAMINATION - A computer system. The computer system including a processor and memory unit coupled to the processor, the memory unit containing instructions that when executed by the processor implement a method for monitoring a solution in a tank used to fabricate integrated circuits, the method comprising the computer implemented steps of: (a) collecting data indicating of an amount of copper in a region of a substrate of a monitor, the monitor comprising an N-type region in a silicon substrate, the region abutting a top surface of the substrate, the monitor having been submerged in the solution for a preset time; (b) comparing the data to a specification for copper content of the solution; (c) if the data indicates a copper content exceeds a limit of the specification for copper, indicating a corrective action is required to prevent copper contamination of the integrated circuits; and (d) repeating steps (a) through (c) periodically. | 04-02-2009 |
20090317972 | METHOD OF FORMING A METAL SILICIDE LAYER, DEVICES INCORPORATING METAL SILICIDE LAYERS AND DESIGN STRUCTURES FOR THE DEVICES - Methods of forming metal silicide layers. The methods include: forming a silicon-rich layer between dielectric layers; contacting the silicon-rich layer with a metal layer and heating the silicon rich-layer and the metal layer to diffuse metal atoms from the metal layer into the silicon layer to form a metal silicide layer. | 12-24-2009 |
20090317973 | METHOD OF FORMING A METAL SILICIDE LAYER, DEVICES INCORPORATING METAL SILICIDE LAYERS AND DESIGN STRUCTURES FOR THE DEVICES - Electronic devices and design structures of electronic devices containing metal silicide layers. The devices include: a thin silicide layer between two dielectric layers, at least one metal wire abutting a less than whole region of the silicide layer and in electrical contact with the silicide layer. | 12-24-2009 |
20110086442 | COPPER CONTAMINATION DETECTION METHOD AND SYSTEM FOR MONITORING COPPER CONTAMINATION - A method of monitoring copper contamination. The method includes method, comprising: (a) ion-implanting an N-type dopant into a region of single-crystal silicon substrate, the region abutting a top surface of the substrate; (c) activating the N-type dopant by annealing the substrate at a temperature of 500° C. or higher in an inert atmosphere; (c) submerging, for a present duration of time, the substrate into an aqueous solution, the aqueous solution to be monitored for copper contamination; and (d) determining an amount of copper adsorbed from the aqueous solution by the region of the substrate. | 04-14-2011 |
Patent application number | Description | Published |
20100052053 | SOI BODY CONTACT USING E-DRAM TECHNOLOGY - A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a body contact disposed under the body/channel region and in the insulator layer. The body contact electrically connects with and contacts with the body/channel region of the semiconductor device and the substrate, to thereby form an ohmic contact and to eliminate floating body effects. | 03-04-2010 |
20110027962 | TRENCH DECOUPLING CAPACITOR FORMED BY RIE LAG OF THROUGH SILICON VIA (TSV) ETCH - A trench decoupling capacitor is formed using RIE lag of a through silicon via (TSV) etch. A method includes etching a via trench and a capacitor trench in a wafer in a single RIE process. The via trench has a first depth and the capacitor trench has a second depth less than the first depth due to RIE lag. | 02-03-2011 |
20110177659 | SOI BODY CONTACT USING E-DRAM TECHNOLOGY - A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a body contact disposed under the body/channel region and in the insulator layer. The body contact electrically connects with and contacts with the body/channel region of the semiconductor device and the substrate, to thereby form an ohmic contact and to eliminate floating body effects. | 07-21-2011 |
20110177660 | DEEP TRENCH CAPACITOR FOR SOI CMOS DEVICES FOR SOFT ERROR IMMUNITY - A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a deep trench capacitor disposed under the body/channel region of the semiconductor device. The deep trench capacitor electrically connects with and contacts the body/channel region of the semiconductor device, and is located adjacent to the gate of the semiconductor device. The semiconductor structure increases a critical charge Qcrit, thereby reducing a soft error rate (SER) of the semiconductor device. | 07-21-2011 |
Patent application number | Description | Published |
20110009318 | Transdermal Compositions and Methods for Treatment of Fibromyalgia and Chronic Fatigue Syndrome - Compositions and methods for alleviating the symptoms associated with chronic fatigue syndrome and fibromyalgia syndrome are provided. The compositions are based on use of a transdermal gel formulation delivery system for androgens, either alone or in combination with other hormones. | 01-13-2011 |
20110118227 | Methods for the Treatment of Fibromyalgia and Chronic Fatigue Syndrome - The invention relates to methods for the treatment of fibromyalgia and chronic fatigue syndrome by administration of a transdermally applied androgen composition. The treatment is both safe and effective for treating fibromyalgia-related pain and fatigue, as well as chronic fatigue syndrome. | 05-19-2011 |
20120130199 | Methods for Treating Chronic or Unresolvable Pain and/or Increasing the Pain Threshold in a Subject and Pharmaceutical Compositions for Use Therein - The invention relates to a method of reducing chronic inflammatory pain in a human subject with androgen deficiency symptoms comprising transdermally administering a pain-reducing amount of a composition comprising a bioactive androgen to the subject on a daily basis. The invention relates to a method of increasing the pain threshold of a human subject having symptoms of androgen deficiency comprising transdermally administering a composition comprising a pain threshold-increasing amount of a bioactive androgen to the subject with androgen deficiency symptoms on a daily basis. The invention may be used to treat males and females in order to alleviate chronic inflammatory pain or to raise the subject's pain threshold. The invention also relates to increasing the levels of endogenous opioid peptides in a human subject by administering an androgen composition to the subject. | 05-24-2012 |
20140018339 | METHODS FOR TREATING CHRONIC OR UNRESOLVABLE PAIN AND/OR INCREASING THE PAIN THRESHOLD IN A SUBJECT AND PHARMACEUTICAL COMPOSITIONS FOR USE THEREIN - Methods are provided for reducing chronic inflammatory pain, increasing the levels of endogenous opioid peptides, as well as increasing the pain threshold of a subject having symptoms of androgen deficiency, comprising transdermally administering a composition comprising a bioactive androgen on a daily basis. In addition, the invention also relates to increasing the levels of endogenous opioid peptides in a human subject by administering an androgen composition to the subject. The invention also encompasses administration of a composition consisting essentially of an androgen for the treatment of chronic inflammatory pain, and for increasing the pain-threshold in a subject. | 01-16-2014 |
20140031326 | METHODS FOR THE TREATMENT OF FIBROMYALGIA AND CHRONIC FATIGUE SYNDROME - The invention relates to methods for the treatment of fibromyalgia and chronic fatigue syndrome by administration of a transdermally applied androgen composition. The treatment is both safe and effective for treating fibromyalgia-related pain and fatigue, as well as chronic fatigue syndrome. | 01-30-2014 |
Patent application number | Description | Published |
20120006369 | EXPANDABLE ISO SHELTERS - An expandable shelter having an expanded configuration and a collapsed configuration in which the shelter has the approximate dimensions of a standard International Organization for Standardization (ISO) freight container. The expandable shelter includes first and second substantially parallel corner posts disposed at a first end of the shelter. The expandable shelter also includes a ramp coupled with hinges at the first end of the shelter and is configured to fit securely on the interior of the first and second corner posts when in a closed configuration in which the ramp is disposed between the first and second corner posts. The expandable shelter has sufficient strength to withstand the forces of at least eight similar shelters stacked on top of the shelter. | 01-12-2012 |
20120037198 | SHELTER HAVING A PROTECTIVE LAYER - A hard walled shelter has first and second substantially parallel corner posts. The hard walled shelter also has an upper frame support extending between first ends of the corner posts and a lower frame support extending between second ends of the corner posts. The hard walled shelter additionally has a moveable wall. The moveable wall has a lower portion hinged at the lower frame support and an upper portion that fits securely on the interior of the corner posts when the moveable wall is in a closed configuration. When the moveable wall is in an open configuration the moveable wall is disposed away from the hard walled shelter to form an opening in the shelter. The hard walled shelter also has a coupling that extends around the perimeter of the opening in the shelter. | 02-16-2012 |
20120037621 | MECHANISM FOR A CONTAINER ASSEMBLY - A mechanism for raising or lowering a sidewall of a container. The mechanism has a shaft that extends across a substantial width of the container adjacent an upper frame support. The shaft has two spools fixedly attached to opposing ends of the shaft. The mechanism has two cables each having one end secured to an associated one of the spools, an opposing end secured to the sidewall, and a length wrapped around the spool and extending between the spool and sidewall. The mechanism has a drive for rotating the shaft to unwrap a portion of the cable allowing for the sidewall to rotate away from the container in response to gravity, and to wrap a portion of the cable around the spool, causing the sidewall to rotate toward the container. | 02-16-2012 |
20120037622 | ADAPTER PLATE FOR A CONTAINER ASSEMBLY - An adapter plate for a container unit that can be coupled to at an additional container unit to form an intermodal container having the approximate dimensions of a standard ISO container. The intermodal container can be handled by a medium tactical vehicle with a load handling system. The container unit has first and second substantially parallel corner posts, an upper frame support extending between first ends of the corner posts, a lower frame support extending between second ends of the corner posts, and a connection block disposed adjacent the second ends of the corner posts. The adapter plate is disposed adjacent the connection block. A proximal end of the adapter plate is connected to the connection block and positioned generally flush with an outer facing surface of the connection block. A distal end of the adapter is angled to connect to an outer surface of the lower frame support. | 02-16-2012 |
20120151851 | EXPANDABLE ISO SHELTERS - An expandable shelter having an expanded configuration and a collapsed configuration in which the shelter has the approximate dimensions of a standard International Organization for Standardization (ISO) freight container. The expandable shelter includes first and second substantially parallel corner posts disposed at a first end of the shelter. The expandable shelter also includes a ramp coupled with hinges at the first end of the shelter and is configured to fit securely on the interior of the first and second corner posts when in a closed configuration in which the ramp is disposed between the first and second corner posts. The expandable shelter has sufficient strength to withstand the forces of at least eight similar shelters stacked on top of the shelter. | 06-21-2012 |
20140001786 | FOLDABLE FLOOR ASSEMBLY FOR AN EXPANDABLE SHELTER | 01-02-2014 |