Weng, Hsinchu City
Cheng-Hui Weng, Hsinchu City TW
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20120299184 | SYSTEM AND METHOD FOR MONITORING COPPER BARRIER LAYER PRECLEAN PROCESS - A monitor wafer for use in monitoring a preclean process and method of making same are described. One embodiment is a monitor wafer comprising a silicon base layer; a capping layer disposed on the silicon base layer; and a barrier layer disposed on the USG layer. The monitor wafer further comprises a copper (“Cu”) seed layer disposed on the barrier layer; and a thick Cu layer disposed on the Cu seed layer. | 11-29-2012 |
20140264864 | INTEGRATED CIRCUIT STRUCTURE AND FORMATION - One or more integrated circuit structures and techniques for forming such integrated circuit structures are provided. The integrated circuit structures comprise a conductive structure that is formed within a trench in a dielectric layer on a substrate. The conductive structure is formed over a barrier layer formed within the trench, or the conductive structure is formed over a liner formed over the barrier layer. At least some of the dielectric layer, the barrier layer, the liner and the conductive structure are removed, for example, by chemical mechanical polishing, such that a step height exists between a top surface of the substrate and a top surface of the dielectric layer. Removing these layers in this manner removes areas where undesired interlayer peeling is likely to occur. A conductive cap is formed on the conductive structure. | 09-18-2014 |
Cheng Yen Weng, Hsinchu City TW
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20110037631 | DAC CALIBRATION - Mechanisms to calibrate a digital to analog converter (DAC) of an SDM (sigma delta modulator) are disclosed. An extra DAC element in addition to the DAC is used to function in place of a DAC element under calibration. A signal (e.g., a random sequence of −1 and +1) is injected to the DAC element under calibration, and the estimated error and compensation are acquired. | 02-17-2011 |
20110037632 | ADC CALIBRATION - An analog to digital convertor (ADC) includes a plurality of comparators one of which is referred to as an auxiliary comparator (e.g., comparator “Aux”). This comparator Aux is calibrated in the background while other comparators function as usual. Once having been calibrated, the comparator Aux replaces a first comparator, which becomes a new comparator Aux, is calibrated, and replaces the second comparator. This second comparator becomes the new comparator Aux, is calibrated, and replaces the third comparator, etc., until all comparators are calibrated. In effect, at any one point in time, a comparator may be calibrated as desire while other comparators and thus the ADC are operating as usual. | 02-17-2011 |
20120133536 | DAC CALIBRATION - Mechanisms to calibrate a digital to analog converter (DAC) of an SDM (sigma delta modulator) are disclosed. An extra DAC element in addition to the DAC is used to function in place of a DAC element under calibration. A signal (e.g., a random sequence of −1 and +1) is injected to the DAC element under calibration, and the estimated error and compensation are acquired. | 05-31-2012 |
20120212361 | SWITCHED-CAPACITOR CIRCUIT WITH LOW SIGNAL DEGRADATION - A switched-capacitor circuit is disclosed. The switched-capacitor circuit includes a comparator having a first and second input, a first and second sampling capacitor, and a first and second switching circuitry. The first switching circuitry charges the first and second sampling capacitor with an input signal. The second switching circuitry selectively couples the first sampling capacitor with a reference voltage and selectively couples the second sampling capacitor and the first and second input of the comparator to a common voltage. The comparator performs a compare of the input signals against the reference voltage, and outputs a signal. | 08-23-2012 |
20120249351 | ADC CALIBRATION - An analog-to-digital converter (ADC) including a plurality of comparators connected to the ADC. The ADC further includes a first pair of terminals and a second pair of terminals connected to each of the plurality of comparators. The ADC further includes a first pair of switches coupled to each of the first pair of terminals and a second pair of switches coupled to each of the second pair of terminals, where the first and second pair of switches are configured to alternate a corresponding comparator between normal operation and a calibration configuration. Comparators other than the corresponding comparator are configured for normal operation if the corresponding comparator is configured to be calibrated. | 10-04-2012 |
20130015876 | APPARATUS AND METHOD FOR MEASURING DEGRADATION OF CMOS VLSI ELEMENTSAANM LAI; Fang-Shi JordanAACI Chia YiAACO TWAAGP LAI; Fang-Shi Jordan Chia Yi TWAANM LU; Chih-ChengAACI Tainan CityAACO TWAAGP LU; Chih-Cheng Tainan City TWAANM LIN; Yung-FuAACI Hsinchu CityAACO TWAAGP LIN; Yung-Fu Hsinchu City TWAANM HSUEH; Hsu-FengAACI Tainan CityAACO TWAAGP HSUEH; Hsu-Feng Tainan City TWAANM CHANG; Chin-HaoAACI Hsinchu CityAACO TWAAGP CHANG; Chin-Hao Hsinchu City TWAANM WENG; Cheng YenAACI Hsinchu CityAACO TWAAGP WENG; Cheng Yen Hsinchu City TWAANM MHALA; Manoj M.AACI HsinchuAACO TWAAGP MHALA; Manoj M. Hsinchu TW - The reliability of an integrated circuit is inferred from the operational characteristics of sample metal oxide semiconductor (MOS) devices switchably coupled to drain/source bias and gate input voltages that are nominal, versus voltage and current conditions that elevate stress and cause temporary or permanent degradation, e.g., hot carrier injection (HCI), bias temperature instability (BTI, NBTI, PBTI), time dependent dielectric breakdown (TDDB). The MOS devices under test (preferably both PMOS and NMOS devices tested concurrently or in turn) are configured as current sources in the supply of power to a ring oscillator having cascaded inverter stages, thereby varying the oscillator frequency as a measure of the effects of stress on the devices under test, but without elevating the stress applied to the inverter stages. | 01-17-2013 |
20130141260 | PIPELINE ANALOG-TO-DIGITAL CONVERTER - A pipelined ADC includes a first, second, and third pairs of comparators. The first pair of comparators compare an input voltage to a first positive reference voltage and to a first negative reference voltage. The second pair of comparators compare the input voltage to a second positive reference voltage and to a second negative reference voltage. Each comparator of the first and second pairs of comparators outputs a digital signal to an encoder. A third pair of comparators compares the input voltage to a third positive reference voltage and to a third negative reference voltage, and a comparator compares the input voltage to ground. The comparator and each comparator of the third pair of comparators is configured to output respective digital signals to an encoder. A multiplying digital-to-analog converter outputs a voltage based on the input voltage, an output from the encoder, and an output of the random number generator. | 06-06-2013 |
20150097710 | ADC CALIBRATION - An analog-to-digital converter (ADC) includes a plurality of comparators connected to the ADC. The ADC further includes a plurality of switches, wherein switches connected to a corresponding comparator of the plurality of comparators are configured to alternate the corresponding comparator between normal operation and a calibration configuration. The ADC further includes at least one comparator of the plurality of comparators other than the corresponding comparator is configured for normal operation if the corresponding comparator is configured for calibration. | 04-09-2015 |
Chih-Horng Weng, Hsinchu City TW
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20090296950 | SIGNAL PROCESSING SYSTEM HAVING A PLURALITY OF HIGH-VOLTAGE FUNCTIONAL BLOCKS INTEGRATED INTO INTERFACE MODULE AND METHOD THEREOF - A signal processing system and related method are disclosed. The signal processing system includes a signal processing module, powered by a low supply voltage, for processing signals; and an interface module, coupled to the signal processing module, powered by a high supply voltage, for outputting signals generated from the signal processing module; wherein the interface module comprises a plurality of high-voltage functional blocks integrated therein, and each of the functional blocks is configured to perform a predetermined interface functionality. In this way, the bill-of-material (BOM) cost can be reduced. | 12-03-2009 |
Chih-Lun Weng, Hsinchu City TW
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20100008308 | LINK ADAPTION IN WIRELESS COMMUNICATIONS - Methods and systems for providing generalized link adaptation in an orthogonal frequency-division multiple access wireless communications network can include determining a number of desired resource blocks (RBs) for each user of a plurality of users; calculating a maximal channel gain G | 01-14-2010 |
Chi-Hsiang Weng, Hsinchu City TW
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20140266087 | START-UP CIRCUIT FOR VOLTAGE REGULATION CIRCUIT - Among other things, techniques and systems are provided to pre-charge a node of a primary circuit, such as a voltage regulator or bandgap voltage reference, via a start-up circuit. The node is charged to a specified voltage during a pre-charge operation that occurs while the primary-circuit is powered-off. The pre-charge operation comprises discharging a voltage from the node during a first portion of the pre-charge operation and re-charging the node to the specified voltage during a second portion of the pre-charge operation. In some embodiments, the specified voltage is substantially equivalent to a switching voltage of a drive transistor of the primary circuit. | 09-18-2014 |
Chi-Jung Weng, Hsinchu City TW
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20090103830 | Method of Simulating the Star Cross Effect of a Light Source and Electronic Apparatus Using The Same - A method of simulating the star cross effect of a light source and an electronic apparatus using the method are disclosed. The method comprises the following steps: setting an image processing parameter; obtaining an image information with the electronic apparatus; analyzing the image information to select each usable point light source; and conducting image processing of the star cross effect to each point light source. | 04-23-2009 |
20090154835 | Method for Rotating An Image and Digital Cameras Using The Same - A method for rotating an image and digital cameras using the same are disclosed. The method comprises: determining whether to auto-rotate an original image according to a rotate initial instruction; if yes, calculating a slope angle of the original image to rotate a first specific angle, wherein the slope angle is substantially equal to the first specific angle; if not, rotating the original image with a second specific angle according to at least a rotating instruction; and forming a rotated image. | 06-18-2009 |
Chou-Chin Weng, Hsinchu City TW
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20130130422 | FABRICATING METHOD OF LIGHT EMITTING DEVICE AND FORMING METHOD OF ORGANIC LAYER - A fabricating method of a light emitting device is provided. In the fabricating method, a substrate having a first electrode layer is provided. An organic film solution that includes an organic material, a solid medium, and a solvent is provided. The solid medium is capable of sublimation, and the organic material and the solid medium are mixed into the solvent. An organic film is formed on the first electrode layer by using the organic film solution. The solvent and the solid medium are removed to form an organic functional layer that has the organic material. A second electrode layer is formed on the organic functional layer. | 05-23-2013 |
Jen-Chung Weng, Hsinchu City TW
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20080309818 | IMAGE-CLOCK ADJUSTING CIRCUIT AND METHOD - An image-clock adjusting circuit is provided and includes a phase comparator, a clock controller, and a timing generator. The phase comparator receives a power source signal and a vertical synchronous signal and compares a phase of the power source signal with that of the first vertical synchronous signal for producing at least a phase comparison signal. The clock controller receives the phase comparison signal and the vertical synchronous signal, produces a pixel clock signal and intermittently adjusts a clock width of the pixel clock signal. The timing generator receives the pixel clock signal and adjusts the vertical synchronous signal into an adjusted vertical synchronous signal being nearly in phase with the power source signal. Therefore, The effect suppressing the phenomenon of the color rolling with the simpler circuit is accomplished. | 12-18-2008 |
Jen-Hsin Weng, Hsinchu City TW
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20130132649 | Flash Memory Controller and Method for Generating a Driving Current for Flash Memories - The invention provides a flash memory controller. In one embodiment, the flash memory controller is coupled to a plurality of flash memories, and comprises a driving current generator and a processor. The driving current generator generates a driving current to drive the flash memories. The processor calculates the total number of flash memories, determines a driving current value according to the total number of flash memories, and directs the driving current generator to generate the driving current with a level greater than or equal to the driving current value. The driving current value is determined by the processor to be increased with an increase of the total number of flash memories. | 05-23-2013 |
Ko-Yun Weng, Hsinchu City TW
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20120219015 | REGISTER SYSTEM AND METHOD FOR UTILIZING A REGISTER UNIT - A register system includes a register unit and a control unit. The register unit is utilized for storing a first data packet, wherein the register unit has an end flag. The control unit is coupled to the register unit, for indicating a designated information and an end position of the first data packet by using the end flag. | 08-30-2012 |
Kuo-Yao Weng, Hsinchu City TW
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20090314366 | FLUIDIC DEVICE - A fluidic device is provided for sealing a proper amount of fluid with a brittle material. By moving an adsorbate through an external adsorption force, the brittle material for pre-sealing is broken, and the fluid flows out to interact with the external environment to generate a pump reaction. In addition, the invention may also be used for storing a liquid reagent in a device for a long time. Thereby, the fluidic device can be made small and portable. | 12-24-2009 |
20120280432 | METHOD FOR MANUFACTURING BIOABSORBABLE STENTS - A method for manufacturing a bioabsorbable stent and an apparatus for doing the same are disclosed. The method includes providing a polymer resin, melting the polymer resin to form a molten hollow parison, cooling the molten hollow parison to form a hot hollow parison, elongating the hot hollow parison, expanding the hot hollow parison by feeding a compressed gas into the hot hollow parison to form a stent preform, and patterning the stent preform to form a bioabsorbable stent. | 11-08-2012 |
20130299587 | OPTICAL REGISTRATION CARRIER - A carrier with the optical registration function is disclosed. The carrier allows the registration of inspected results of the sampling images of the sample to the corresponding address codes of the address coding site of the carrier. | 11-14-2013 |
20140046401 | RETINAL PROSTHESIS - A retinal prosthesis including a microelectrode array, a polymer layer and a layer of bioactive molecule is provided. The microelectrode includes a plurality of microelectrodes. The polymer layer partly encapsulates the microelectrode array, in which the microelectrodes are exposed on the surface of the polymer layer. The layer of bioactive molecules is immobilized on the surface of the microelectrode. | 02-13-2014 |
20140124373 | PARTICLE MANIPULATION SYSTEM AND PROJECTION DEVICE - A particle manipulation system and a projection device are provided. The projection device includes an image source and a projection lens. The image source provides an image beam. The projection lens is disposed on a light path of the image beam and includes a zoom lens set and a focusing lens set. The zoom lens set is disposed on the light path of the image beam from the image source and includes at least two lens groups disposed in sequence on the light path of the image beam. The focusing lens set is disposed on the light path of the image beam. The zoom lens set is disposed between the image source and the focusing lens set. A photoconductor chip is disposed on the light path of the image beam from the projection lens. | 05-08-2014 |
Shao-Wei Weng, Hsinchu City TW
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20130335413 | SYSTEM AND METHOD FOR ESTIMATING CONSTRUCTION DURATION - A system and method for estimating construction duration. The system includes a three-dimensional (3D) building information model (BIM) module, a duration estimation module, and a 4D BIM module. The 3D BIM module constructs a 3D BIM based on inputted modeling instructions and generates quantity information corresponding to the 3D BIM. The duration estimation module calculates duration information for construction work based on inputted construction condition information and the quantity information of the 3D BIM produced. The 4D BIM module constructs a 4D BIM based on the 3D BIM and the duration information. Thus, the present invention can automatically calculate the quantity of building materials, estimate the construction duration, establish a construction progress table, and demonstrate the construction progress of the 4D BIM in an animated way, replacing the traditional way of manually processing information for duration estimation. | 12-19-2013 |
Tsu-Pin Weng, Hsinchu City TW
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20140026058 | Establishing System and Method for Establishing Application Program Having Capability Controlling Input and Output Interface for Mobile Computing Device - The present invention relates to an establishing system and a method for providing a user accessing an establishing platform having a user interface through a browser for establishing application program for mobile computing device and having capability controlling input and output interface for a mobile computing device, wherein the input and output interface adopts a wireless communication protocol for bi-directionally communicating with an external device, the user interface comprises a input and output interface management module configured to provide the user to define the contents for the wireless communication protocol. | 01-23-2014 |
Tuz-Wen Weng, Hsinchu City TW
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20150371862 | METHOD OF FORMING PATTERN - A method of forming a pattern including following steps is provided. A wafer is provided, wherein the wafer includes a plurality of wafer interior dies and a plurality of wafer edge dies. A first pattern is formed on each of the wafer interior dies, and a second pattern is formed on each of the wafer edge dies. A method of forming the first patterns includes performing at least two exposure processes, and a method of forming the second patterns includes performing at least one of the at least two exposure processes, wherein a number of the exposure processes performed for forming the second patterns is less than a number of the exposure processes performed for forming the first patterns. | 12-24-2015 |
Vincent Weng, Hsinchu City TW
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20120057615 | INFRARED CLINICAL THERMOMETER ABLE TO COMMUNICATE - An infrared clinical thermometer able to communicate is disclosed. The infrared clinical thermometer has a control module arranged inside a casing and electrically connected with an infrared body temperature sensation unit, a communication interface, a measurement key, a transmission key, and a power key. When intending to measure body temperature, the user presses the power key to start the infrared clinical thermometer. According to the signal of the measurement key, the control module controls the infrared body temperature sensation unit to detect body temperature. When intending to transmit measurement results, the user links the communication interface to the computer via a detachable communication cable and then presses the transmission key or common key. Then, the control module transmits measurement results to the computer. The infrared clinical thermometer is detachably linked to the computer and thus easy to measure temperature and transmit data. | 03-08-2012 |
Wu-An Weng, Hsinchu City TW
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20140120690 | Streamlined Process for Vertical Semiconductor Devices - The present disclosure provides a streamlined approach to forming vertically structured devices such as deep trench capacitors. Trenches and a contact plate bridging the trenches are formed using one lithographic process. A hard mask is formed over the substrate and etched through the mask to form two or more closely spaced trenches. The hard mask is then reduced by an isotropic etch process. The etch removes the hard mask preferentially between the trenches. Chemical mechanical polishing removes the conductive material down to the remaining hard mask layer, whereby conductive material remains in mask openings and forms a conductive bridge across the trenches. | 05-01-2014 |
20140159197 | SELF-ALIGNED DEEP TRENCH CAPACITOR, AND METHOD FOR MAKING THE SAME - A method for forming a trench capacitor includes providing a substrate of a semiconductor material having a hard mask layer; etching the hard mask layer and the substrate to form at least one trench extending into the substrate; and performing pull-back etching on the hard mask layer. In the pull-back etching, a portion of the hard mask layer defining and adjacent to side walls of an opening of the at least one trench is removed. A resulting opening on the hard mask layer has a width dimension larger than a width dimension of an opening of the at least one trench extending into the substrate. The method further comprises doping the semiconductor material defining upper surfaces and sidewalls of the at least one trench to form a doped well region. | 06-12-2014 |
20140327109 | DEEP TRENCH CAPACITOR MANUFACTURED BY STREAMLINED PROCESS - The present disclosure provides a deep trench capacitor device. A first capacitor electrode is made up of a doped region of semiconductor substrate in which two or more trenches are arranged. A second capacitor electrode is made up of a continuous body of conductive material. The continuous body of conductive material includes a lower body portion filling the two or more trenches and an upper body portion extending continuously over the lower body portion. The upper body portion extends upwardly out of the trenches by a non-zero distance. A capacitor dielectric liner is arranged in the two or more trenches to separate the first and second capacitor electrodes. The capacitor dielectric liner extends continuously out of the two or more trenches along outer sidewalls of the upper body portion. | 11-06-2014 |
Wu Der Weng, Hsinchu City TW
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20090281745 | Monitoring Plasma Induced Damage During Semiconductor Wafer Processes - A plasma damage detection test structure is disclosed. The plasma damage detection test structure includes a first antenna, a voltage source, a ground reference, a first transistor comprising a first source, a first gate, and a first drain. The plasma damage detection test structure further includes a second transistor comprising a second source, a second gate, and a second drain. The first gate is conductively coupled to said first antenna, said first drain and said second drain are conductively coupled to said voltage source, and said first source and said second source are conductively coupled to said ground reference. In various embodiments multiple antennas may be used. The antennas may be multiple configurations, such as a symmetric arrangement or asymmetric arrangement. In various embodiments, multiple transistors in parallel or cross-couple arrangements may be used. | 11-12-2009 |
Wu Kun Weng, Hsinchu City TW
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20120079289 | SECURE ERASE SYSTEM FOR A SOLID STATE NON-VOLATILE MEMORY DEVICE - A secure erase system for a solid state memory device is disclosed. A memory area provides a data block for storing data and a key block for storing at least one key. A translation unit maps a logical address to a physical address associated with the memory area. An encryption unit encrypts plaintext data to be written to the memory area with the associated key and decrypts the encrypted data to be read by a host with the associated key. The key associated with a logical erase group to be secure erased is deleted after receiving a command requesting to erase the data associated with the logical erase group. | 03-29-2012 |
Yu-Shih Weng, Hsinchu City TW
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20130202460 | FLUIDICS PUMPING DEVICE - A fluidics pumping device including a body and a driving assembly is provided. The body has a chamber, a channel, an inlet and an outlet. The channel goes through the chamber and connects with the inlet and the outlet. The driving assembly is disposed in the chamber, and the driving assembly has a contact surface exposed in the channel. The contact surface is suitable for moving along an extension direction of the channel, for driving a fluid in the channel. | 08-08-2013 |