Patent application number | Description | Published |
20080237855 | Ball grid array package and its substrate - A BGA package and a substrate for the package are disclosed. A chip is disposed on a top surface of the substrate. A plurality of solder balls are disposed on a plurality of ball pads formed on a bottom surface of the substrate. The substrate has at least a core layer with a plurality of corner cavities filled with low-modulus materials as stress buffer. Additionally, some of the ball pads at the corners of the substrate are disposed under the corner cavities. | 10-02-2008 |
20080272489 | Package substrate and its solder pad - A semiconductor chip substrate with solder pad includes: a core layer and at least one conductive structure formed on the surface of the core layer; an insulation layer with at least one patterned opening covering the conductive structure, wherein the patterned opening has a center portion and a plurality of wing portions on the peripheral edge of the center portion to define the exposed area of the conductive structure as the solder pad. The solder pad with wing will improve the adhesion effect between the solder pad and the solder ball. | 11-06-2008 |
20090026599 | Memory module capable of lessening shock stress - A memory module capable of lessening shock stresses, primarily comprises a multi-layer printed circuit board (PCB), a plurality of memory packages, and a stress-buffering layer. The memory packages are disposed at least on one of the rectangular surfaces of the PCB. The stress-buffering layer is disposed at least on both short sides of the PCB and extended to the two rectangular surfaces to reduce the impact stresses. Preferably, the stress-buffering layer is further disposed on the other long side of the PCB opposite to the one with disposed gold fingers. | 01-29-2009 |
20090091027 | Semiconductor package having restraining ring surfaces against soldering crack - A semiconductor package with crack-restraining ring surfaces is revealed, primarily comprising a chip carrier, a chip disposed on the chip carrier, and a plurality of belfry-like bumps. The belfry-like bumps are disposed on a plurality of corresponding conductive pads on the bottom surface of the chip carrier as external terminals. Each belfry-like bump has at least a crack-restraining ring surface parallel to the conductive pads and between the top of the belfry-like bump and the conductive pad to prevent the spreading of the soldering cracks and to enhance the soldering strengths at the micro contacts to achieve higher package reliability. | 04-09-2009 |
20090096070 | Semiconductor package and substrate for the same - A semiconductor package is revealed with a special designed substrate. The substrate has a plurality of fingers, a dummy metal pattern, and at least a peripheral slot penetrating through the substrate. The dummy metal pattern is aligned to two opposing sides of the peripheral slot and is electrically isolated from the fingers. A chip is disposed on the substrate and is electrically connected to the fingers. An encapsulant is completely filled the peripheral slot. The peripheral slot can enhance the mold flow and eliminate the mold flash. The shape of the dummy metal pattern aligned to the peripheral slot is used to offer stiffening edges to prevent the substrate from warpage and from breakage at peripheries, to enhance the thermal stress resistance due to thermal cycles, and to avoid damages to the chip. | 04-16-2009 |
20090127679 | POP (Package-On-Package) device encapsulating soldered joints between externals leads - A POP (Package-On-Package) semiconductor device with encapsulating protection of soldered joints between the external leads, primarily comprises a plurality of stacked semiconductor packages and dielectric coating. Each semiconductor package includes at least a chip, a plurality of external leads of leadframe, and an encapsulant where the external leads are exposed and extended from a plurality of sides of the encapsulant. Terminals of a plurality external leads of a top semiconductor package are soldered to the soldered regions of the corresponding external leads of a bottom semiconductor package. The dielectric coating is disposed along the sides of the encapsulant of the bottom semiconductor package to connect the soldered points between the external leads and to partially or completely encapsulate the soldering materials so that the stresses between the soldered joints can be dispersed and no electrical shorts happen. | 05-21-2009 |
20090137069 | Chip packaging process including simpification and mergence of burn-in test and high temperature test - A chip packaging process integrates a burn-in test or a high temperature test to simplify overall packaging and testing process flow. One or more chips are disposed on one or more units of a substrate strip where the substrate strip has a plurality of electrical open sections at the plating lines to electrically isolate the external pads between different units. After electrical connection and encapsulation, a burn-in test is executed at the same time of a post mold curing step, with a high-temperature testing if necessary. Therefore, the chips on the substrate strip has been gone through the burn-in test during the encapsulant is completely cured at the post mold curing step and the burn-in test is finished before the singulation step to reduce the overall testing time. | 05-28-2009 |
20090160038 | Semiconductor package with leads on a chip having multi-row of bonding pads - A LOC leadframe-based semiconductor package includes a chip with multiple rows of bonding pads. At least a bus bar is attached to the chip and is disposed between a first row of bonding pads and the fingers of the leads. A plurality of bonding wires electrically connect the first row of bonding pads to the fingers of the leads. The portion of the bus bar attached to the active surface of the chip includes a bent section bent away from the fingers. A long bonding wire electrically connects one of a second row of bonding pads to one of the fingers of the leads by overpassing the bent section. Therefore, the distance between the long bonding wire and the bus bar is increased to avoid electrical short between the long bonding wire and the bus bar and to enhance the quality of electrical connections of the LOC semiconductor package. | 06-25-2009 |
20090160041 | Substrate package structure - A substrate package structure is disclosed herein. The substrate package structure includes a packaging substrate provided with a plurality of chip carriers set at one surface of the packaging substrate, wherein those chip carriers are formed by intersecting a plurality of cutting streets; a plurality of through holes set at those cutting streets and set around those chip carriers; and a plurality of molding areas set on another surface of the packaging substrate and opposite to those chip carriers, wherein those molding areas are adjacent to those through holes. Hence, those through holes may be flowed by the molding compound to form a plurality of molding bumps around those chip carriers so as to improve the crack problem of the chip and/or the substrate. | 06-25-2009 |
20090173528 | CIRCUIT BOARD READY TO SLOT - A circuit substrate ready to slot is revealed, primarily comprising a board base with slot-reserved area. A plurality of bonding fingers, a plating bus loop, and a plurality of plating lines disposed on the bottom surface of the board base. The bonding fingers are located adjacent to but outside the slot-reserved area and the plating bus loop is located inside the slot-reserved area. The plating lines connect the bonding fingers to the plating bus lines. The plating bus loop includes two side bars closer to the long sides of the slot-reserved area than the bonding fingers to the long sides. Accordingly, the lengths of the plating lines within the slot-reserved area are shortened. It is possible to solve the issues of metal burs and shifting of the remaining plating lines when routing a slot along the peripheries of the slot-reserved area. Moreover, the plating current can evenly distribute to improve the plating qualities on the surfaces of the bonding fingers. | 07-09-2009 |
20090176334 | Method for forming a die-attach layer during semiconductor packaging processes - Disclosed is a method for forming a die-attach layer during semiconductor packaging processes. A chip carrier includes a substrate core and a stiffener. Top surface of the substrate core includes a plurality of die-attaching units and a peripheral area enclosed by the stiffener. A non-planar printing stencil is also provided. When the non-planar printing stencil is pressed against the chip carrier, the non-planar printing stencil is compliantly in contact with the substrate core and the stiffener and a plurality of printing openings of the non-planar printing stencil exposes the substrate core within the die-attaching units. During stencil printing, die-attach material fills in the printing openings to directly adhere to the substrate core. Therefore, the warpage of the substrate core is restrained to avoid bleeding of die-attach material so that die-attach materials can be formed as a die-attach layer with a uniform thickness on core-exposed chip carrier with lower costs. Additionally, the chip carrier will not be deformed during semiconductor packaging processes. | 07-09-2009 |
20090243099 | WINDOW TYPE BGA SEMICONDUCTOR PACKAGE AND ITS SUBSTRATE - A window-type BGA semiconductor package is revealed, primarily comprising a substrate with a wire-bonding slot, a chip disposed on a top surface of the substrate, and a plurality of bonding wires passing through the wire-bonding slot. A plurality of plating line stubs are formed on a bottom surface of the substrate, connect the bonding fingers on the substrate and extend to the wire-bonding slot. The bonding wires electrically connect the bonding pads of the chip to the corresponding bonding fingers of the substrate. The plating line stubs are compliant to the wire-bonding paths of the bonding wires correspondingly connected at the bonding fingers, such as parallel to the overlapped arrangement, to avoid electrical short between the plating line stubs and the bonding wires with no corresponding relationship of electrical connections. | 10-01-2009 |
20090283878 | LEAD-ON-CHIP SEMICONDUCTOR PACKAGE AND LEADFRAME FOR THE PACKAGE - A LOC semiconductor package with the leadframe for the package is revealed. The LOC semiconductor package primarily comprises a plurality of leadframe's leads, at least a tie bar, a chip, and an encapsulant encapsulating the components mentioned above. Each lead has a bonding finger. The tie bar has a dummy finger where the dummy finger is linearly disposed at one side of the disposition area of the bonding fingers. The chip has an active surface with the bonding fingers. When the dummy finger and the bonding fingers are disposed above the active surface by a die-attaching layer, the dummy finger is adjacent to one edge of the active surface. The bonding fingers are electrically connected with the bonding pads. The dummy finger will bear the concentrated stresses to avoid the bonding fingers on the active surface to delamination or break due to external stresses and to avoid the interference to the layout of the leads. | 11-19-2009 |
20090302485 | LAMINATE SUBSTRATE AND SEMICONDUCTOR PACKAGE UTILIZING THE SUBSTRATE - A laminated substrate and the semiconductor package utilizing the substrate are revealed. The laminated substrate primarily comprises a core layer, a first metal layer and a first solder mask disposed on the bottom surface of the core layer, and a second metal layer and a second solder mask disposed on the top surface of the core layer. The two solder masks have different CTEs to compensate potential substrate warpage caused by thermal stresses. Therefore, the manufacturing cost of the substrate can be reduced without adding extra stiffeners nor changing thicknesses of semiconductor packages to suppress substrate warpage during packaging processes. Especially, a die-attaching layer partially covers the second solder mask by printing and is planar after pre-curing for zero-gap die-attaching. | 12-10-2009 |
20100019373 | UNIVERSAL SUBSTRATE FOR SEMICONDUCTOR PACKAGES AND THE PACKAGES - A universal substrate for semiconductor packages and the package are revealed. The universal substrate comprises a substrate core, two peripheral rows of bonding fingers and a central row of redistribution fingers disposed on the substrate core, and a solder mask formed on the substrate core. The redistribution fingers are located between two rows of the bonding fingers. The solder mask has an opening to expose the redistribution fingers. A plurality of exhaust grooves are formed on the solder mask without penetrating through the solder mask where one end of the exhaust grooves connects to the opening and the other end extends toward the edges of the substrate core without connecting to another opening exposing the bonding fingers to be the releasing channels of gases generated during die-attaching processes. When disposing larger IC chips, the issue of residue bubbles trapped in the covered opening and the issue of contaminations of bonding fingers by the die-bonding adhesives can be eliminated. In one of the embodiment, the traces connecting to the redistribution fingers can be overlapped with the exhaust grooves without being exposed from the solder mask to enhance the design flexibility of the exhaust grooves. | 01-28-2010 |
20100038118 | SUBSTRATE PANEL - A substrate panel primarily comprises a plurality of substrate strips arranged in an array, one or more current input lines, a plurality of cascaded lines connecting between the substrate strips, and a current input buffer gate. Current input lines connect a current input side of the substrate panel to the adjacent substrate strips. The current input buffer gate has a frame around the substrate strips and a plurality of meshes where the frame intersects with the current input lines and the meshes intersect with the cascaded lines with both ends of the meshes connecting to the frame. Therefore, the current can be evenly distributed to each substrate strip during plating processes to improve the issues of different plating thicknesses and different plating roughness caused by different current densities and to protect the internal circuits inside the substrate strips from the damages due to current surges and unstable voltages. | 02-18-2010 |
20100127362 | SEMICONDUCTOR PACKAGE HAVING ISOLATED INNER LEAD - A semiconductor package with isolated inner lead(s) is revealed. A chip is disposed on a leadframe segment and encapsulated by an encapsulant. The leadframe segment includes a plurality of leads, an isolated lead, and an external lead where each lead has an internal portion and an external portion. The isolated inner lead is completely formed inside the encapsulant and the external lead is partially formed inside and extended outside the encapsulant. At least one of the internal portions of the leads is located between the isolated inner lead and the external lead. Two fingers are formed at two opposing ends of the isolated inner lead without covering by the chip. One of the fingers imitates a plurality of fingers of the leads to arrange along a first side of the chip. The other finger of the isolated inner lead and a finger of the external lead are arranged along a second side of the chip. A jumping wire electrically connecting the isolated inner lead and the external lead is adjacent to the second side to achieve the redistribution of pin assignments without affecting wire-bonding. Especially, this package can be applied for multi-chip stacking. | 05-27-2010 |
20120228759 | SEMICONDUCTOR PACKAGE HAVING INTERCONNECTION OF DUAL PARALLEL WIRES - A semiconductor package having dual parallel wires is disclosed. A chip is attached on a substrate where the chip and the substrate are electrically connected by a bonding wire. The bonding wire consists of a first metal wire, a second metal wire, and an insulating body where the insulating body encapsulates the first and the second metal wires to make both metal wires parallel to each other. The insulating body forms a constant gap between the first and the second metal wires so that both metal wires do not contact to each other. Therefore, the electrical performance of the package can greatly be enhanced with the same productivity. | 09-13-2012 |
20140167231 | LEADFRAME-TYPE SEMICONDUCTOR PACKAGE HAVING EMI SHIELDING LAYER CONNECTED TO GROUND - Disclosed is a leadframe-type semiconductor package having an EMI shielding layer connected to ground, comprising a leadframe, a chip, an encapsulant, and an EMI shielding layer. The encapsulant has two lead-extending sides and two leadless sides. The EMI shielding layer covers at least one surface of the encapsulant and the leadless sides. A metal tie bar coupling to the die attach pad of the leadframe has a cut end aligned with and exposed on one of the leadless sides. A ground lead also has a cut end aligned with and exposed on one of the leadless sides Since the EMI shielding layer covers and electrically connects the cut ends of the metal tie bar and the ground lead, the die pad with its metal tie bar of the leadframe is connected to the ground lead through external electrical connection outside the encapsulant to allow the die pad having ground potential. | 06-19-2014 |