Wei-Jung
Wei Jung Chan, Pingjhen City TW
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20090284955 | CONNECTOR, BACKLIGHT MODULE, LIQUID CRYSTAL DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE BACKLIGHT MODULE - A backlight module includes a housing and at least one connector. The housing includes a bottom plate, which includes an upper surface, a lower surface and at least one through opening. The connector includes an upper portion, a middle portion and a lower portion, wherein the lower portion is disposed within the through hole and is provided with an electrically conductive contact, the middle portion is located between the upper portion and the lower portion, and the middle portion is disposed over the upper surface of the bottom plate. | 11-19-2009 |
Wei Jung Chen, Hsinchu TW
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20080315307 | HIGH VOLTAGE DEVICE - A high voltage device includes a semiconductor substrate and a gate. The semiconductor substrate includes a first doped region having a first conductive type, a second doped region having a second conductive type, a third doped region having the second conductive type, a fourth doped region surrounding the third doped region and having the second conductive type, and a fifth doped region surrounding the third doped region and having the second conductive type. The gate is disposed between two spacers to separate the second doped region from the third doped region, so as to control the conduction of the second doped region and the third doped region. In the high voltage device, the fifth doped region surrounds the third doped region, so as to strengthen the coverage for the third doped region and improve the ion concentration uniformity on the bottom of the third doped region to reduce leakage current. | 12-25-2008 |
Wei Jung Lee, Taipei City TW
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20110043091 | Structure of LED Lamps - An improved structure of LED lamps, which tightly fixes the LED to circuit board through indirectly pressing. The improved structure of LED lamps comprises of a lamp shell, the inside of which can be configured with a first circuit board attached with LED, and a second circuit board attached with positive and negative terminals; in particular: on either ends of the lamp shell, a supporting structure and a back cover can be configured. Screws can go through the screw hole(s) which are on the back cover and lock into the support pillar(s) of the supporting structure. Through the screwing, the supporting structure pulls the LED, first circuit board and lamp shell altogether, and provides an indirectly pressure on the first circuit board further makes the first circuit board attach tightly to the platform of lamp shell, accomplishing tight and accurate positioning effect, better heat transfer and heat conduction effect. | 02-24-2011 |
Wei Jung Wang, Shanghai CN
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20140248524 | BATTERIES AND METHODS OF MANUFACTURING BATTERIES - Disclosed is a paper battery that includes a cellulosic substrate having absorbed thereon an electrolyte material and first and second barrier substrates disposed on opposite sides of the cellulosic substrate. Each of the first and second barrier substrates have an electrode printed thereon. At least one of the first and second barrier substrates includes first and second polymer layers. Further disclosed is a method of manufacturing a paper battery that includes the steps of absorbing an electrolyte material onto a cellulosic substrate and disposing on opposite sides of the cellulosic substrate first and second barrier substrates. Each of the first and second barrier substrates have an electrode printed thereon. At least one of the first and second barrier substrates includes first and second polymer layers. | 09-04-2014 |
Wei-Jung Chen, Hsinchu County TW
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20140160609 | SHORT-CIRCUIT PROTECTION CIRCUIT OF LIGHT EMITTING DIODE AND SHORT-CIRCUIT PROTECTION METHOD THEREOF AND LIGHT EMITTING DIODE DRIVING APPARATUS USING THE SAME - A short-circuit protection circuit of a light emitting diode (LED) is for protecting a plurality of LED strings from a short-circuit condition. The short-circuit protection circuit includes a short-circuit protection unit and a control unit. The short-circuit protection unit is coupled to the plurality of LED strings to execute a short-circuit protection. The control unit coupled to the short-circuit protection unit and the LED strings is configured to control the short-circuit protection unit according to at least one of a feedback voltage and a compensation voltage, so as to determine whether to trigger the short-circuit protection. The feedback voltage is generated from a cross voltage of one of the LED strings, and the compensation voltage is generated according to a comparison result between the feedback voltage and a reference voltage for controlling a power supply of the LED strings. | 06-12-2014 |
20140168041 | REFERENCE VOLTAGE GENERATOR OF GATE DRIVING CIRCUIT AND REFERENCE VOLTAGE GENERATING METHOD - A reference voltage generator of a gate driving circuit is provided. The reference voltage generator includes a temperature sensing unit, a level clamp unit, a gain adjusting unit and a computing circuit. The temperature sensing unit generates a temperature sensing voltage in response to an environmental temperature. The level clamp unit is coupled to the temperature sensing unit and providing a difference signal in response to the temperature sensing voltage. The gain adjusting unit is used to provide a temperature compensating gain and a first reference level. The gain adjusting unit adjusts the temperature compensating gain and the first reference level according to a control command. The computing circuit is coupled to the level clamp unit and the gain adjusting unit to provide a reference voltage in response to the temperature compensating gain, the first reference level and the difference signal. | 06-19-2014 |
Wei-Jung Chen, Taipei City TW
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20110020462 | NEW USE OF HISTONE DEACETYLASE INHIBITORS IN CHANGING MRJP3 PROTEIN IN ROYAL JELLY - The invention provides a method of changing a ratio of 68 to 64 kDa protein of MRJP3 in a royal jelly, a method of producing a royal jelly comprising MRJP3 having a changed ratio of 68 to 64 kDa protein relative to a control royal jelly and the royal jelly produced thereform. Also provided is a method of promoting the growth of the larva of a queen bee comprising feeding the larva of the queen bee a royal jelly of the invention. Further provided is a method of producing bee larva, pupa and queen bees with sizes larger than normal. | 01-27-2011 |
20130293477 | ELECTRONIC APPARATUS AND METHOD FOR OPERATING THE SAME - An electronic apparatus and an operation method thereof are provided. The electronic apparatus has a sensor module. A space operation mode is enabled when an operation object is detected in a sensor space by the sensor module. A controlling function corresponding to one of a plurality of using spaces divided from the sensor space in which the operation object is located is enabled. Movement information of the operation object is detected by the sensor module, and an operation action corresponding to the enabled controlling function is executed. | 11-07-2013 |
Wei-Jung Chen, Taipei TW
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20140288166 | USE OF HISTONE DEACETYLASE INHIBITORS IN CHANGING MRJP3 PROTEIN IN ROYAL JELLY - The invention provides a method of changing a ratio of 68 to 64 kDa protein of MRJP3 in a royal jelly, a method of producing a royal jelly comprising MRJP3 having a changed ratio of 68 to 64 kDa protein relative to a control royal jelly and the royal jelly produced thereform. Also provided is a method of promoting the growth of the larva of a queen bee comprising feeding the larva of the queen bee a royal jelly of the invention. Further provided is a method of producing bee larva, pupa and queen bees with sizes larger than normal. | 09-25-2014 |
Wei-Jung Chen, Tainan City TW
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20130264515 | POLISHING SLURRY COMPOSITION - Provided is a polishing slurry composition, including a non-ionic surfactant represented by the following formula (1) | 10-10-2013 |
Wei-Jung Chiu, Miao-Li County TW
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20150261026 | LIQUID CRYSTAL DISPLAY PANEL AND PIXEL CELL CIRCUIT SOLVING COLOR SHIFT PROBLEM - A liquid crystal display panel includes multiple pixel units each connected to a data line and a gate line. The pixel unit defines a first region and a second region. A first liquid crystal capacitor is disposed in the first region. A first transistor is disposed in the first region and is connected between the data line and the first liquid crystal capacitor, and has a control electrode connected to the gate line. A second liquid crystal capacitor is disposed in the second region. A second transistor is disposed in the second region and is connected between the data line and the second liquid crystal capacitor, and has a control electrode connected to the gate line. A third transistor is disposed in the second region and is connected between a common voltage and the second transistor and has a control electrode connected to the gate line. | 09-17-2015 |
Wei-Jung Chung, Pingtung City TW
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20110097831 | Method of Manufacturing a Vertical Type Light-Emitting Diode - In a method of manufacturing a vertical type light-emitting diode, a multilayered structure of group III nitride semiconductor compounds is epitaxy deposited on an irregular surface of a substrate. The substrate is then removed to expose an irregular surface of the multilayered structure corresponding to the irregular surface of the substrate. A portion of the exposed irregular surface of the multilayered structure is then etched for forming an electrode contact surface on which an electrode layer is subsequently formed. With this method, no specific planarized region is required on the irregular surface of the substrate. As a result, planarization treatment of the substrate is not necessary. The same substrate with the irregular surface can be reused for fabricating vertical and horizontal light-emitting diodes. | 04-28-2011 |
20110163293 | Vertical Light-Emitting Diode and Manufacture Method Thereof - The present application describes a vertical light-emitting diode (VLED) and its manufacture method that use the combination of a reflective layer, a transparent conducting layer and transparent dielectric layer as structural layers for promoting uniform current distribution and increasing light extraction. In the VLED, a transparent conducting layer is formed on a first outer surface of a stack of multiple group III nitride semiconductor layers. A transparent dielectric layer is then formed on a side of the transparent conducting layer opposite the side of the multi-layer structure. A first electrode structure is then formed on the transparent dielectric layer in electrical contact with the transparent conducting layer via a plurality of contact windows patterned through the transparent dielectric layer. The transparent conducting layer and the transparent dielectric layer are used as structural layers for improving light extraction. | 07-07-2011 |
Wei-Jung Hong, Tao-Yuan County TW
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20110285047 | METHOD AND DEVICE OF FABRICATING THREE DIMENSIONAL SCAFFOLDS - A method of fabricating three-dimensional scaffolds includes the steps of forming a plurality of bubbles by providing a gelatin solution and a gas stream passing through a bubble production device, gathering the bubbles, cooling the bubbles, crosslinking the bubbles by adding the agent with aldehyde group, and breaking at least some of the bubbles to be interconnected to form a three-dimensional porous materials. | 11-24-2011 |
Wei-Jung Lin, Taipei TW
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20080199978 | System and method for film stress and curvature gradient mapping for screening problematic wafers - A method of testing a wafer after a current top layer is formed over the wafer. Stress data is collected for the wafer after forming the current top layer. The stress data is derived from changes in wafer curvature. The stress data includes: stress-xx in an x direction and stress-yy in a y direction for each area of a set of finite areas on the wafer, the stress-xx and stress-yy both being derived from wafer-curvature-change-xx in the x direction for each area of the set of finite areas and from wafer-curvature-change-yy in the y direction for each area of the set of finite areas; and the stress-xy being derived from wafer-curvature-change-xy, wherein wafer-curvature-change-xy is a change in wafer twist in the x-y plane for each area of the set of finite areas. A stress gradient vector (and/or its norm) is calculated and used to evaluate the investigating single or multiple accumulated layer. | 08-21-2008 |
20090040767 | Recognition Module - A recognition module is applied in recognizing counterfeit of a card or a face of the card. The recognition module includes a sealed space, a light emitter, a light receiver and a transparent dustproof plate. The sealed space has two corresponding side inclinations and a transparent cover surface which covers two side inclinations. The light emitter and the light receiver are disposed to the side inclinations respectively. Moreover, the transparent dustproof plate is disposed on the light emitter and the light receiver, and is also disposed under the transparent cover surface. Accordingly, the light emitter and/or the light receiver may not be covered by dust and mists to influence the light-transmitting/receiving efficiency. The recognition rate regarding counterfeit of the card or the face of the card may not be influenced either. | 02-12-2009 |
20150021757 | Systems and Methods for Reducing Contact Resistivity of Semiconductor Devices - Systems and methods are provided for reducing a contact resistivity associated with a semiconductor device structure. A substrate including a semiconductor region is provided. One or more dielectric layers are formed on the semiconductor region, the one or more dielectric layers including an element. A gaseous material is applied on the one or more dielectric layers to change a concentration of the element in the one or more dielectric layers. A contact layer is formed on the one or more dielectric layers to generate a semiconductor device structure. The semiconductor device structure includes the contact layer, the one or more dielectric layers, and the semiconductor region. A contact resistivity associated with the semiconductor device structure is reduced by changing the concentration of the element in the one or more dielectric layers. | 01-22-2015 |
20150147880 | CONTACT STRUCTURE AND FORMATION THEREOF - A semiconductor device and methods of formation are provided. A semiconductor device includes an annealed cobalt plug over a silicide in a first opening of the semiconductor device, wherein the annealed cobalt plug has a repaired lattice structure. The annealed cobalt plug is formed by annealing a cobalt plug at a first temperature for a first duration, while exposing the cobalt plug to a first gas. The repaired lattice structure of the annealed cobalt plug is more regular or homogenized as compared to a cobalt plug that is not so annealed, such that the annealed cobalt plug has a relatively increased conductivity or reduced resistivity. | 05-28-2015 |
20150243565 | METHODS OF FORMING LOW RESISTANCE CONTACTS - Methods for forming electrical contacts are provided. First and second FETs are formed over a semiconductor substrate. Openings are etched in a dielectric layer formed over the substrate, where the openings extend to source and drain regions of the FETs. A hard mask is formed over the source and drain regions of FETs. A first portion of the hard mask is removed, where the first portion is formed over the source and drain regions of the first FET. First silicide layers are formed over the source and drain regions of the first FET. A second portion of the hard mask is removed, where the second portion is formed over the source and drain regions of the second FET. Second silicide layers are formed over the source and drain regions of the second FET. A metal layer is deposited within the openings to fill the openings. | 08-27-2015 |
20160035629 | METHODS OF FORMING LOW RESISTANCE CONTACTS - Methods for forming electrical contacts are provided. First and second FETs are formed over a semiconductor substrate. Openings are etched in a dielectric layer formed over the substrate, where the openings extend to source and drain regions of the FETs. A hard mask is formed over the source and drain regions of FETs. A first portion of the hard mask is removed, where the first portion is formed over the source and drain regions of the first FET. First silicide layers are formed over the source and drain regions of the first FET. A second portion of the hard mask is removed, where the second portion is formed over the source and drain regions of the second FET. Second silicide layers are formed over the source and drain regions of the second FET. A metal layer is deposited within the openings to fill the openings. | 02-04-2016 |
Wei-Jung Lin, Taipei City TW
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20080237750 | Silicided metal gate for multi-threshold voltage configuration - A PMOS (p-channel metal oxide semiconductor) device having at low voltage threshold MOSFET (MOS field effect transistor) with an improved work function and favorable DIBL (drain-induced barrier lowering) and SCE (short channel effect) characteristics, and a method for making such a device. The PMOS device includes a gate structure that is disposed on a substrate and includes a silicided gate electrode. The silicide is preferably nickel-rich and includes a peak platinum concentration at or near the interface between the gate electrode and a dielectric layer that separates the gate electrode from the substrate. The platinum peak region is produced by a multi-step rapid thermal annealing or similar process. The PMOS device may also include two such MOSFETs, one of which is boron-doped and one of which is not. | 10-02-2008 |
20090166768 | Semiconductor device with metal silicides having different phases - A fully silicided gate with a selectable work function includes a gate dielectric over the substrate, a first metal silicide layer over the gate dielectric, and a second metal silicide layer wherein the first metal silicide has a different phase then the second metal silicide layer. The metal silicide layers comprises at least one alloy element. The concentration of the alloy element on the interface between the gate dielectric and the metal silicide layers influence the work function of the gate. | 07-02-2009 |
20120012903 | METHOD FOR MAKING A DISILICIDE - Methods for fabricating a semiconductor device are disclosed. A metal-rich silicide and/or a mono-silicide is formed on source/drain (S/D) regions. A millisecond anneal is provided to the metal-rich silicide and/or the mono-silicide to form a di-silicide with limited spikes at the interface between the silicide and substrate. The di-silicide has an additive which can lower the electron Schottky barrier height. | 01-19-2012 |
20130034944 | METHOD FOR MAKING A DISILICIDE - Methods for fabricating a semiconductor device are disclosed. A metal-rich silicide and/or a mono-silicide is formed on source/drain (S/D) regions. A millisecond anneal is provided to the metal-rich silicide and/or the mono-silicide to form a di-silicide with limited spikes at the interface between the silicide and substrate. The di-silicide has an additive which can lower the electron Schottky barrier height. | 02-07-2013 |
20150048511 | Opening Fill Process and Structure Formed Thereby - Methods of forming conductive structures and the conductive structures are disclosed. A method includes forming an opening in a dielectric layer over a substrate, performing a cleaning process on the dielectric layer with the opening, forming a nucleation layer in the opening, etching the nucleation layer in the opening, and forming a conductive material in the opening and on the nucleation layer after the etching. An upper portion of the opening is distal from the substrate, and a lower portion of the opening is proximate the substrate. After the etching, a thickness of an upper portion of the nucleation layer in the upper portion of the opening is less than a thickness of a lower portion of the nucleation layer in the lower portion of the opening. | 02-19-2015 |
20150179512 | Method of Integrated Circuit Fabrication - A method of fabricating an integrated circuit (IC) is disclosed. The method includes providing a substrate having a conductive feature. A dielectric layer is formed over the substrate, having an opening to expose the conductive feature. A tungsten (W) capping layer is formed over the conductive feature in the opening without using fluorine-containing gases. A bulk W layer is formed over the W capping layer. | 06-25-2015 |
20150206881 | Formation Of Silicide Contacts In Semiconductor Devices - Methods of forming silicide contacts in semiconductor devices are presented. An exemplary method comprises providing a semiconductor substrate having an n-type field effect transistor (nFET) region and a p-type field effect transistor (pFET) region; performing a pre-amorphized implantation (PAI) process to an n-type doped silicon (Si) feature in on the nFET region and a p-type doped silicon germanium (SiGe) feature in the pFET region, thereby forming an n-type amorphous silicon (a-Si) feature and a p-type amorphous silicon germanium (a-SiGe) feature; depositing a metal layer over each of the a-Si and a-SiGe features; performing an annealing process on the semiconductor device with a temperature ramp-up rate tuned according to a silicide growth rate difference between the n-type a-Si and the p-type a-SiGe features. During the annealing process the n-type a-Si and the p-type a-SiGe features are completely consumed, and amorphous silicide features are formed in the nFET and pFET regions. | 07-23-2015 |
20150380509 | IMPROVED FORMATION OF SILICIDE CONTACTS IN SEMICONDUCTOR DEVICES - Methods of forming silicide contacts in semiconductor devices are presented. An exemplary method comprises providing a semiconductor substrate having an n-type field effect transistor (nFET) region and on a p-type field effect transistor (pFET) region; performing a pre-amorphized implantation (PAI) process to an n-type doped silicon (Si) feature in on the nFET region and a p-type doped silicon germanium (SiGe) feature in the pFET region, thereby forming an n-type amorphous silicon (a-Si) feature and a p-type amorphous silicon germanium (a-SiGe) feature; depositing a metal layer over each of the a-Si and a-SiGe features; performing an annealing process on the semiconductor device with a temperature ramp-up rate tuned according to a silicide growth rate difference between the n-type a-Si and the p-type a-SiGe features. During the annealing process the n-type a-Si and the p-type a-SiGe features are completely consumed, and amorphous silicide features are formed in the nFET and pFET regions. | 12-31-2015 |
20160049362 | Interconnect Structure and Method of Forming the Same - An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a contact layer over a substrate; a dielectric layer over the contact layer, wherein the dielectric layer has an opening, the opening exposing a portion of the contact layer; a silicide layer over the exposed portion of the contact layer; a barrier layer along sidewalls of the opening; an alloy layer over the barrier layer; a glue layer over the alloy layer; and a conductive plug over the glue layer. | 02-18-2016 |
Wei-Jung Lin, Hsin-Chu TW
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20160126102 | DIRECTIONAL PRE-CLEAN IN SILICIDE AND CONTACT FORMATION - A method includes etching a dielectric layer to form an opening, with an underlying region underlying the dielectric layer exposed to the opening, and performing a bombardment to bombard a surface region of the underlying region through the opening. After the bombardment, the surface region is reacted with a process gas to form a reaction layer. An anneal is then performed to remove the reaction layer. | 05-05-2016 |