Patent application number | Description | Published |
20140065740 | Single Phosphor Layer Photonic Device for Generating White Light or Color Lights - A photonic device generates light from a full spectrum of lights including white light. The device includes two or more LEDs grown on a substrate, each generating light of a different wavelength and separately controlled. A light-emitting structure is formed on the substrate and apportioned into the two or more LEDs by etching to separate the light-emitting structure into different portions. At least one of the LEDs is coated with a phosphor material so that different wavelengths of light are generated by the LEDs while the same wavelength of light is emitted from the light-emitting structure. | 03-06-2014 |
20140117454 | FinFET with Dummy Gate on Non-Recessed Shallow Trench Isolation (STI) - An embodiment fin field effect transistor (FinFET) device includes fins formed from a semiconductor substrate, a non-recessed shallow trench isolation (STI) region disposed between the fins, and a dummy gate disposed on the non-recessed STI region. | 05-01-2014 |
20140206156 | FINFET DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a fin structure disposed over the substrate. The fin structure includes one or more fins. The semiconductor device further includes an insulation material disposed on the substrate. The semiconductor device further includes a gate structure disposed on a portion of the fin structure and on a portion of the insulation material. The gate structure traverses each fin of the fin structure. The semiconductor device further includes a source and drain feature formed from a material having a continuous and uninterrupted surface area. The source and drain feature includes a surface in a plane that is in direct contact with a surface in a parallel plane of the insulation material, each of the one or more fins of the fin structure, and the gate structure. | 07-24-2014 |
20140206166 | FINFET DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a fin structure including one or more fins disposed on the substrate. The semiconductor device further includes a dielectric layer disposed on a central portion of the fin structure and traversing each of the one or more fins. The semiconductor device further includes a work function metal disposed on the dielectric layer and traversing each of the one or more fins. The semiconductor device further includes a strained material disposed on the work function metal and interposed between each of the one or more fins. The semiconductor device further includes a signal metal disposed on the work function metal and on the strained material and traversing each of the one or more fins. | 07-24-2014 |
20140252442 | Method and Structure for Vertical Tunneling Field Effect Transistor and Planar Devices - The present disclosure provides one embodiment of a method of forming a tunnel field effect transistor (TFET). The method includes forming a semiconductor mesa on a semiconductor substrate; performing a first implantation to the semiconductor substrate and the semiconductor mesa to form a drain of a first type conductivity; forming a first dielectric layer on the semiconductor substrate and sidewall of the semiconductor mesa; forming a gate stack on the sidewall of the semiconductor mesa and the first dielectric layer; forming a second dielectric layer on the first dielectric layer and the gate stack; and forming, on the semiconductor mesa, a source having a second type conductivity opposite to the first type conductivity. The gate stack includes a gate dielectric and a gate electrode on the gate dielectric. The source, drain and gate stack are configured to form the TFET. | 09-11-2014 |
20140264289 | Structure and Method for Vertical Tunneling Field Effect Transistor with Leveled Source and Drain - The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first semiconductor mesa formed on the semiconductor substrate within the first region; a second semiconductor mesa formed on the semiconductor substrate within the second region; and a field effect transistor (FET) formed on the semiconductor substrate. The FET includes a first doped feature of a first conductivity type formed in a top portion of the first semiconductor mesa; a second doped feature of a second conductivity type formed in a bottom portion of the first semiconductor mesa, the second semiconductor mesa, and a portion of the semiconductor substrate between the first and second semiconductor mesas; a channel in a middle portion of the first semiconductor mesa and interposed between the source and drain; and a gate formed on sidewall of the first semiconductor mesa. | 09-18-2014 |
20150054039 | FinFet Device with Channel Epitaxial Region - The present disclosure relates to a Fin field effect transistor (FinFET) device having epitaxial enhancement structures, and an associated method of fabrication. In some embodiments, the FinFET device has a semiconductor substrate having a plurality of isolation regions overlying the semiconductor substrate. A plurality of three-dimensional fins protrude from a top surface of the semiconductor substrate at locations between the plurality of isolation regions. Respective three-dimensional fins have an epitaxial enhancement structure that introduces a strain into the three-dimensional fin. The epitaxial enhancement structures are disposed over a semiconductor material within the three-dimensional fin at a position that is more than 10 nanometers above a bottom of an adjacent isolation region. Forming the epitaxial enhancement structure at such a position provides for sufficient structural support to avoid isolation region collapse. | 02-26-2015 |
20150069474 | Isolation Structure of Fin Field Effect Transistor - The disclosure relates to a fin field effect transistor (FinFET). An exemplary FinFET comprises a substrate comprising a major surface; a fin structure protruding from the major surface comprising a lower portion comprising a first semiconductor material having a first lattice constant; an upper portion comprising the first semiconductor material, wherein a bottom portion of the upper portion comprises a dopant with a first peak concentration; a middle portion between the lower portion and upper portion, wherein the middle portion comprises a second semiconductor material having a second lattice constant different from the first lattice constant; and an isolation structure surrounding the fin structure, wherein a portion of the isolation structure adjacent to the bottom portion of the upper portion comprises the dopant with a second peak concentration equal to or greater than the first peak concentration. | 03-12-2015 |
20150102411 | FinFET with Buried Insulator Layer and Method for Forming - A fin structure suitable for a FinFET and having a buried insulator layer is disclosed. In an exemplary embodiment, a semiconductor device comprises a substrate with a first semiconductor material and having a fin structure formed thereupon. The fin structure includes a lower region proximate to the substrate, a second semiconductor material disposed on the lower region, a third semiconductor material disposed on the second semiconductor material, and an insulating material selectively disposed on the second semiconductor material such that the insulating material electrically isolates a channel region of the fin structure and further such that the insulating material exerts a strain on the channel region. The semiconductor device further comprises an isolation feature disposed adjacent to the fin structure. | 04-16-2015 |
20150219448 | WAFER ALIGNMENT MARK SCHEME - A wafer alignment apparatus includes a light source, a light detection device, and a rotation device configured to rotate a first wafer and a second wafer. The light source is configured to provide a first light directed to the first wafer and a second light directed to the second wafer. The light detection device is configured to detect reflected light intensity from the first wafer to find a position of at least one wafer alignment mark of the first wafer and to detect reflected light intensity from the second wafer to find a position of at least one wafer alignment mark of the second wafer. | 08-06-2015 |
20150236114 | SEMICONDUCTOR DEVICE AND FORMATION THEREOF - A semiconductor device and method of formation are provided herein. A semiconductor device includes a barrier including carbon over a fin, the fin including a doped region. The semiconductor device includes an epitaxial (Epi) cap over the barrier, the Epi cap including phosphorus. The barrier inhibits phosphorus diffusion from the Epi cap into the fin as compared to a device that lacks such a barrier. The inhibition of the phosphorus diffusion reduces a short channel effect, thus improving the semiconductor device function. | 08-20-2015 |
20150357445 | STRUCTURE AND METHOD FOR VERTICAL TUNNELING FIELD EFFECT TRANSISTOR WITH LEVELED SOURCE AND DRAIN - The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first semiconductor mesa formed on the semiconductor substrate within the first region; a second semiconductor mesa formed on the semiconductor substrate within the second region; and a field effect transistor (FET) formed on the semiconductor substrate. The FET includes a first doped feature of a first conductivity type formed in a top portion of the first semiconductor mesa; a second doped feature of a second conductivity type formed in a bottom portion of the first semiconductor mesa, the second semiconductor mesa, and a portion of the semiconductor substrate between the first and second semiconductor mesas; a channel in a middle portion of the first semiconductor mesa and interposed between the source and drain; and a gate formed on sidewall of the first semiconductor mesa. | 12-10-2015 |
20160087103 | FinFET with Buried Insulator Layer and Method for Forming - A fin structure suitable for a FinFET and having a buried insulator layer is disclosed. In an exemplary embodiment, a semiconductor device comprises a substrate with a first semiconductor material and having a fin structure formed thereupon. The fin structure includes a lower region proximate to the substrate, a second semiconductor material disposed on the lower region, a third semiconductor material disposed on the second semiconductor material, and an insulating material selectively disposed on the second semiconductor material such that the insulating material electrically isolates a channel region of the fin structure and further such that the insulating material exerts a strain on the channel region. The semiconductor device further comprises an isolation feature disposed adjacent to the fin structure. | 03-24-2016 |
Patent application number | Description | Published |
20080280436 | METHOD FOR FABRICATING AN INDUCTOR STRUCTURE OR A DUAL DAMASCENE STRUCTURE - A method for fabricating an inductor structure or a dual damascene structure is disclosed. First, a dielectric layer is provided. Subsequently, a first etching process is performed on the dielectric layer so as to form a first opening in the dielectric layer. A polymer is also formed in the first opening during the first etching process. Next, a polymer-removing step is performed to remove the polymer. Thereafter, a second etching process is performed on the dielectric layer to form a second opening in the dielectric layer. Furthermore, the first opening and the second opening are filled with a conductive material so as to form an inductor structure or a dual damascene structure. | 11-13-2008 |
20090111268 | REWORKING METHOD FOR INTEGRATED CIRCUIT DEVICES - A reworking method for integrated circuit devices includes the following: providing a substrate having a first base layer and a first dielectric layer formed thereon, performing a first dry etching process to remove the first dielectric layer, performing a CMP process to remove the first base layer, and sequentially reforming a second base layer and a second dielectric layer on the substrate. When certain layers on the IC device have hailed an inspection or when quality defects are found, the defective layer is removed according to the provided reworking method. | 04-30-2009 |
20150037974 | METHOD OF PATTERNING PLATINUM LAYER - A method of patterning a platinum layer includes the following steps. A substrate is provided. A platinum layer is formed on the substrate. An etching process is performed to pattern the platinum layer, wherein an etchant used in the etching process simultaneously includes at least a chloride-containing gas and at least a fluoride-containing gas. | 02-05-2015 |
20160111383 | METHOD OF USING ALUMINUM LAYER AS ETCHING STOP LAYER FOR PATTERNING A PLATINUM LAYER - A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a dielectric layer; forming an aluminum layer on the dielectric layer; forming a platinum layer on the aluminum layer; performing a first etching process to remove part of the platinum layer and part of the aluminum layer for forming a patterned platinum layer; and performing a second etching process to remove part of the aluminum layer exposed by the patterned platinum layer and part of the dielectric layer. | 04-21-2016 |
Patent application number | Description | Published |
20100248398 | E-CHUCK FOR AUTOMATED CLAMPED FORCE ADJUSTMENT AND CALIBRATION - The present disclosure provides a semiconductor manufacturing method. The method includes performing a first process to a wafer; measuring the wafer for wafer data after the first process; securing the wafer on an E-chuck in a processing chamber; collecting sensor data from a sensor embedded in the E-chuck; adjusting clamping forces to the E-chuck based on the wafer data and the sensor data; and thereafter performing a second process to the wafer secured on the E-chuck in the processing chamber. | 09-30-2010 |
20100268367 | METHOD FOR BIN-BASED CONTROL - A method for providing bin-based control when manufacturing integrated circuit devices is disclosed. The method comprises performing a plurality of processes on a plurality of wafer lots; determining a required bin quantity, an actual bin quantity, and a projected bin quantity; comparing the determined required bin quantity with the determined actual bin quantity and determined projected bin quantity; and modifying at least one of the plurality of processes on the plurality of wafer lots if the determined actual bin quantity and determined projected bin quantity fail to satisfy the determined required bin quantity. | 10-21-2010 |
20100292824 | SYSTEM AND METHOD FOR IMPLEMENTING A WAFER ACCEPTANCE TEST ("WAT") ADVANCED PROCESS CONTROL ("APC") WITH NOVEL SAMPLING POLICY AND ARCHITECTURE - System and method for implementing wafer acceptance test (“WAT”) advanced process control (“APC”) are described. In one embodiment, the method comprises performing a key process on a sample number of wafers of a lot of wafers; performing a key inline measurement related to the key process to produce metrology data for the wafers; predicting WAT data from the metrology data using an inline-to-WAT model; and using the predicted WAT data to tune a WAT APC process for controlling a tuning process or a process APC process. | 11-18-2010 |
20100294955 | METHOD AND SYSTEM OF MONITORING E-BEAM OVERLAY AND PROVIDING ADVANCED PROCESS CONTROL - A method for monitoring overlay of a direct-write system. The method includes providing a substrate having a pattern formed thereon by the direct-write system, generating data associated with the substrate pattern, decomposing the data by applying a transformation matrix, and determining an overlay index based on the decomposed data, the overlay index corresponding to a variation component of the substrate pattern relative to a target pattern. | 11-25-2010 |
20110042006 | E-CHUCK WITH AUTOMATED CLAMPED FORCE ADJUSTMENT AND CALIBRATION - The present disclosure describes a semiconductor manufacturing apparatus. The apparatus includes a processing chamber designed to perform a process to a wafer; an electrostatic chuck (E-chuck) configured in the processing chamber and designed to secure the wafer, wherein the E-chuck includes an electrode and a dielectric feature formed on the electrode; a tuning structure designed to hold the E-chuck to the processing chamber by clamping forces, wherein the tuning structure is operable to dynamically adjust the clamping forces; a sensor integrated with the E-chuck and sensitive to the clamping forces; and a process control module for controlling the tuning structure to adjust the clamping forces based on pre-measurement data from the wafer and sensor data from the sensor. | 02-24-2011 |
20110112678 | ADVANCED PROCESS CONTROL FOR NEW TAPEOUT PRODUCT - The present disclosure provides a semiconductor manufacturing method. The method includes providing product data of a product, the product data including a sensitive product parameter; searching existing products according to the sensitive product parameter to identify a relevant product from the existing products; determining an initial value of a processing model parameter to the product using corresponding data of the relevant product; assigning the initial value of the processing model parameter to a processing model associated with a manufacturing process; thereafter, tuning a processing recipe using the processing model; and performing the manufacturing process to a semiconductor wafer using the processing recipe. | 05-12-2011 |
20110238198 | METHOD AND SYSTEM FOR IMPLEMENTING VIRTUAL METROLOGY IN SEMICONDUCTOR FABRICATION - The present disclosure provides a method of fabricating a semiconductor device. The method includes collecting a plurality of manufacturing data sets from a plurality of semiconductor processes, respectively. The method includes normalizing each of the manufacturing data sets in a manner so that statistical differences among the manufacturing data sets are reduced. The method includes establishing a database that includes the normalized manufacturing data sets. The method includes normalizing the database in a manner so that the manufacturing data sets in the normalized database are statistically compatible with a selected one of the manufacturing data sets. The method includes predicting performance of a selected one of the semiconductor processes by using the normalized database. The selected semiconductor process corresponds to the selected manufacturing data set. The method includes controlling a semiconductor processing machine in response to the predicted performance. | 09-29-2011 |
20130144419 | INTEGRATED CIRCUIT MANUFACTURING TOOL CONDITION MONITORING SYSTEM AND METHOD - A system and method for monitoring a process tool of an integrated circuit manufacturing system are disclosed. An exemplary method includes defining zones of an integrated circuit manufacturing process tool; grouping parameters of the integrated circuit manufacturing process tool based on the defined zones; and evaluating a condition of the integrated circuit manufacturing process tool based on the grouped parameters. | 06-06-2013 |
20130144423 | SYSTEMS AND METHODS OF AUTOMATIC BOUNDARY CONTROL FOR SEMICONDUCTOR PROCESSES - A system and method of automatically calculating boundaries for a semiconductor fabrication process. The method includes selecting a first parameter for monitoring during a semiconductor fabrication process. A first set of values for the first parameter are received and a group value of the first set is determined. Each value in the first set of values is normalized. A first weighting factor is selected based on a number of values in the first set. The embodiment also includes generating a first and a second boundary value as a function of the weighting factor, the first set normalized values and the group value of the first set and applying the first and second boundary values to control the semiconductor fabrication process. | 06-06-2013 |
20130150997 | METHOD AND SYSTEM FOR TOOL CONDITION MONITORING - A method and system for removing control action effects from inline measurement data for tool condition monitoring is disclosed. An exemplary method includes determining a control action effect that contributes to an inline measurement, wherein the inline measurement indicates a wafer characteristic of a wafer processed by a process tool; and evaluating the inline measurement without the control action effect contribution to determine a condition of the process tool. | 06-13-2013 |
20130171746 | MULTI-ZONE TEMPERATURE CONTROL FOR SEMICONDUCTOR WAFER - An apparatus and a method for controlling critical dimension (CD) of a circuit is provided. An apparatus includes a controller for receiving CD measurements at respective locations in a circuit pattern in an etched film on a first substrate and a single wafer chamber for forming a second film of the film material on a second substrate. The single wafer chamber is responsive to a signal from the controller to locally adjust a thickness of the second film based on the measured CD's. A method provides for etching a circuit pattern of a film on a first substrate, measuring CD's of the circuit pattern, adjusting a single wafer chamber to form a second film on a second semiconductor substrate based on the measured CD. The second film thickness is locally adjusted based on the measured CD's. | 07-04-2013 |
20130306621 | REAL-TIME CALIBRATION FOR WAFER PROCESSING CHAMBER LAMP MODULES - An apparatus, a system and a method are disclosed. An exemplary apparatus includes a wafer processing chamber. The apparatus further includes radiant heating elements disposed in different zones and operable to heat different portions of a wafer located within the wafer processing chamber. The apparatus further includes sensors disposed outside the wafer processing chamber and operable to monitor energy from the radiant heating elements disposed in the different zones. The apparatus further includes a computer configured to utilize the sensors to characterize the radiant heating elements disposed in the different zones and to provide a calibration for the radiant heating elements disposed in the different zones such that a substantially uniform temperature profile is maintained across a surface of the wafer. | 11-21-2013 |
20140067324 | QUALITATIVE FAULT DETECTION AND CLASSIFICATION SYSTEM FOR TOOL CONDITION MONITORING AND ASSOCIATED METHODS - The present disclosure provides various methods for tool condition monitoring, including systems for implementing such monitoring. An exemplary method includes receiving data associated with a process performed on wafers by an integrated circuit manufacturing process tool; and monitoring a condition of the integrated circuit manufacturing process tool using the data. The monitoring includes evaluating the data based on an abnormality identification criterion, an abnormality filtering criterion, and an abnormality threshold to determine whether the data meets an alarm threshold. The method may further include issuing an alarm when the data meets the alarm threshold. | 03-06-2014 |
20140207271 | TOOL OPTIMIZING TUNING SYSTEMS AND ASSOCIATED METHODS - The present disclosure provides various methods for tuning process parameters of a process tool, including systems for implementing such tuning. An exemplary method for tuning process parameters of a process tool such that the wafers processed by the process tool exhibit desired process monitor items includes defining behavior constraint criteria and sensitivity adjustment criteria; generating a set of possible tool tuning process parameter combinations using process monitor item data associated with wafers processed by the process tool, sensitivity data associated with a sensitivity of the process monitor items to each process parameter, the behavior constraint criteria, and the sensitivity adjustment criteria; generating a set of optimal tool tuning process parameter combinations from the set of possible tool tuning process parameter combinations; and configuring the process tool according to one of the optimal tool tuning process parameter combinations. | 07-24-2014 |
20150162166 | SYSTEM AND METHOD FOR CONTROLLING ION IMPLANTER - A system, a method, and a non-transitory computer readable storage medium for controlling an ion implanter are disclosed herein. The system includes a sample module and a control module. The sample module is configured to generate a summarized value from process data of the ion implanter, and the process data correspond to a control parameter. The control module is configured to tune a control parameter, and the control module performs an ion implantation by releasing tools of the ion implanter in accordance with the control parameter when the summarized value meets a predetermined stability requirement. | 06-11-2015 |
Patent application number | Description | Published |
20090085898 | DATA PROCESSING MODULE FOR GENERATING DITHERED DATA AND METHOD THEREOF - A data processing module for generating dithered data includes a data transforming unit and a dithering unit, wherein the data transforming unit is utilized to transform input data into transformed data containing predetermined data, and the dithering unit is utilized to perform a dithering process on the transformed data to generate the dithered data. By making the display picture of the dithered data contain a fixed pattern corresponding to the predetermined data, the influence on the display picture caused by noise existing in the input data can be efficiently reduced. | 04-02-2009 |
20090085925 | DITHERING MASK AND METHOD OF FORMING THE SAME - A method of forming a dithering mask includes providing a specific sub-dithering mask, and generating a plurality of sub-dithering masks of the dithering mask by adjusting the specific sub-dithering mask. The dithering mask generated by the method includes a plurality of sub-dithering masks, each sub-dithering mask includes (4N)×(4N) dithering values, where N is an integer, and at least two sub-dithering masks of the plurality of sub-dithering masks have different contents. By breaking the regularity in the dithering mask, flickering patterns or visual patterns can be avoided on the screen, thereby raising the displaying quality of the screen. | 04-02-2009 |
20090129698 | METHOD AND DEVICE FOR ELIMINATING IMAGE BLUR BY PIXEL-BASED PROCESSING - A method for eliminating image blur includes: detecting the difference in pixel value between two corresponding pixels in two continuous images to generate a difference value; and adjusting the luminance of the two corresponding pixels according to the difference value, wherein when the difference value exceeds a predetermined value, the luminance of one pixel of the two corresponding pixels is increased and the luminance of the other pixel is decreased. | 05-21-2009 |
Patent application number | Description | Published |
20130236051 | COMPUTER READABLE MEDIA CAN PERFORM INTERFERENCE IMAGE DETERMINING METHOD AND INTERFERENCE IMAGE DETERMINING APPARATUS - A computer readable media having at least one program code recorded thereon. An interference image determining method can be performed when the program code is read and executed. The interference image determining method comprises: (a) controlling a light source to illuminate an object on a detecting surface to generate an image; (b) controlling a sensor to catch a current frame of the image; (c) utilizing an image characteristic included in the current frame to determine a interference image part of the current frame; and (d) updating a defined interference image according to the determined interference image part. | 09-12-2013 |
20140132565 | IMAGE SENSING APPARATUS, OPTICAL TOUCH CONTROL APPARATUS AND MOTION TRACKING APPARATUS UTILIZING THE IMAGE SENSING APPARATUS - An image sensing apparatus, comprising: a control unit; and an image sensor, wherein the control unit controls the image sensor to utilize a first image sensing region to sense a first image to output a first image signal in a first mode, wherein the control unit controls the image sensor to utilize a second image sensing region to sense a second image to output a second image signal in a second mode. The first image sensing region is smaller than a total image sensing region of the image sensor, and the second image sensing region is smaller than the first image sensing region. | 05-15-2014 |
20140210723 | OPTICAL MOUSE APPARATUS AND DATA COMPRESSION METHOD USED IN OPTICAL MOUSE APPARATUS - An optical mouse apparatus includes a light source circuit, a sensing circuit, and a processing circuit. The light source circuit is used for generating and emitting a light signal onto a surface so as to generate a light reflected signal. The sensing circuit is used for estimating an image offset of the optical mouse apparatus. The processing circuit is coupled to the light source circuit and the sensing circuit and used for generating and outputting a control signal to a terminal according to the image offset outputted by the sensing circuit. The sensing circuit is further used for detecting at least one of a moving speed or an offset direction of the image offset of the optical mouse apparatus, so as to dynamically determine whether to compress data of the image offset outputted to the processing circuit, for reducing data amount read by the processing circuit. | 07-31-2014 |
20140240229 | TOUCH CONTROL METHOD AND TOUCH CONTROL APPARATUS - A computer readable recording media comprising at least one program code recorded thereon, a touch control method is performed when the program code is read and executed. The touch control method comprises the following steps: (a) detecting location data for an object relative to a detecting surface to generate at least one displacement data; (b) storing the displacement data to a storage apparatus and outputting the stored displacement data to a target apparatus from the storage apparatus after storing the displacement data for a predetermined time period, when the object touches the detecting surface; and (c) cleaning the stored displacement data when the object leaves the detecting surface. | 08-28-2014 |
20140320409 | OPTICAL FINGER MOUSE EQUIPPED WITH FEEDBACK FUNCTION AND ASSOCIATED CONTROL METHOD - An optical finger mouse includes a housing, a light source, a light guide mechanism, an image sensor, a processor and a feedback module. The housing is arranged for an object to be detected performing a motion control thereon, wherein the object to be detected slides or taps on the housing to perform the motion control. The light source is arranged for generating light. The light guide mechanism is arranged for guiding the light generated by the light source to project on the object to be detected. The image sensor captures reflected light generated from the object to be detected to generate a sensing result. The processor generates detection information according to the sensing result. The feedback module generates feedback according to the detection information. | 10-30-2014 |
20140333540 | OPTICAL NAVIGATION DEVICE WITH DIFFERENT OPTICAL MECHANISMS AND ASSOCIATED METHOD THEREOF - An optical navigation device includes a first optical mechanism, a second optical mechanism, an image sensor, and a controller. The first optical mechanism is arranged for projecting light on a surface to generate a first projection result while the second optical mechanism is arranged for projecting light on the surface to generate a second projection result. The image sensor is arranged for sensing at least one of the first projection result and the second projection result within a sensing range to generate at least one first image sensing result. The controller is coupled to the first optical mechanism, the second optical mechanism and the image sensor, and is arranged for controlling the first optical mechanism and the second optical mechanism according to the first image sensing result. The optical navigation device accordingly performs movement detection. | 11-13-2014 |
Patent application number | Description | Published |
20140191971 | OPTICAL MOUSE APPARATUS BASED ON IMAGE VARIATION AND RELATED METHOD THEREOF - An optical mouse apparatus includes a light source unit, a sensing unit, and a processing unit. The light source unit is arranged for generating and emitting an optical signal, wherein the optical signal is emitted upon a surface, and then reflected to form an optical reflected signal. The sensing unit is arranged for generating a sensed image output according to the optical reflected signal, wherein the sensed image output is utilized for estimating an image displacement of the optical mouse apparatus. The processing unit is coupled to the light source unit and the sensing unit, and arranged for controlling the light source unit to emit the optical signal and determining a operation status of the optical mouse apparatus according to an image variation of at least a partial region of each of consecutive images of the sensed image output. | 07-10-2014 |
20140368433 | ELECTRONIC APPARATUS AND ELECTRONIC SYSTEM THAT CAN SELECT SIGNAL SMOOTHING APPARATUS, AND COMPUTER READABLE MEDIA THAT CAN PERFORM SIGNAL SMOOTHING METHOD THAT CAN SELECT SIGNAL SMOOTHING OPERATION - An electronic apparatus that can utilize a first report rate to generate a first report rate output signal according to an output signal or can utilize a second report rate smaller than the first report rate to generate a second report rate output signal according to the output signal. The electronic apparatus comprises: a first signal smoothing apparatus; a second signal smoothing apparatus having a smooth ability smaller than the first signal smoothing apparatus and a processing unit, for selecting the first signal smoothing apparatus to process the first report rate output signal when the electronic apparatus utilizes the first report rate to generate signal, and for selecting the second signal smoothing apparatus to process the second report rate output signal when the electronic apparatus utilizes the second report rate to generate signal. | 12-18-2014 |
20140372633 | ELECTRONIC SYSTEM AND COMPUTER READABLE RECORDING MEDIA CAN PERFORM REPORT RATE SETTING METHOD - An electronic system that can automatically set a report rate, which comprises: a first electronic apparatus; a second electronic apparatus; a transmitting interface, wherein the second electronic apparatus transmits data to the first electronic apparatus via the transmitting interface; and a processing unit, for automatically setting a report rate of the second electronic apparatus or the transmitting interface according to a type of a software program that the first electronic apparatus executes. | 12-18-2014 |
20150097779 | METHOD OF ADJUSTING SAMPLING PRECISION OF A NAVIGATION DEVICE, RELATED NAVIGATION DEVICE AND RELATED TERMINAL DEVICE - A method of adjusting sampling precision of a navigation device is disclosed in the present invention. The sampling precision represents counts per inch (CPI) or dots per inch (DPI) of the navigation device. The method includes determining a predetermined mode of the navigation device, obtaining resolution of a display, and adjusting the sampling precision according to the resolution and the predetermined mode, so that the sampling precision of the navigation device can be accordingly increased and decreased due to variation of the resolution. | 04-09-2015 |
Patent application number | Description | Published |
20100141033 | EFFICIENT PWM CONTROLLER - This patent discloses an efficient PWM controller for generating a pulse signal in response to a feedback signal, capable of operating in a normal mode or a green mode, comprising: a capacitor for building a saw-tooth signal by current integration, the saw-tooth signal having a ramp-up period and a ramp-down period; a first composite current source for the ramp-up period, detachable into a first constant current source and a first variable current source; and a second composite current source for the ramp-down period, detachable into a second constant current source and a second variable current source; wherein, the first variable current source is attached to the first constant current source and the second variable current source is attached to the second constant current source respectively in the green mode. | 06-10-2010 |
20100315062 | QUASI-RESONANT VALLEY VOLTAGE DETECTING METHOD AND APPARATUS - The present invention discloses a quasi-resonant valley voltage detecting method, comprising the steps of: generating a valley detection signal by detecting a valley of a first quasi-resonant signal; generating a count value by counting the valley detection signal; and determining a level transition instance of a gating signal according to the count value, wherein the level transition instance of the gating signal is pulled back by the valley detection signal to trace the valley of the first quasi-resonant signal. The present invention also provides a quasi-resonant valley voltage detecting apparatus. | 12-16-2010 |
20110062886 | OPEN LOOP LED DRIVING CIRCUIT - The present invention discloses an open loop LED driving circuit, having a turn-on period and a turn-off period, the circuit comprising: a power stage, used to store a magnetic energy supplied from a voltage source during the turn-on period and deliver the magnetic energy to a set of LEDs during the turn-off period; and a control unit, having a turn-off period control terminal coupled to the voltage source, and a channel of which a first terminal is coupled to the power stage and a second terminal is coupled to a reference ground, wherein the channel is switched on at a time according to the voltage of the voltage source to determine the turn-off period. | 03-17-2011 |
20110133705 | INTEGRATED CIRCUIT FOR SYSTEM CALIBRATION - The present invention discloses an integrated circuit for system calibration, applicable to a power supply, comprising: a comparison module, having a feedback input end coupled to a feedback signal and a reference input end coupled to an analog reference signal for delivering a status signal; a detection and control module, for generating a reference signal and a calibration value according to the status signal, wherein the calibration value is derived from the reference signal at an instant when the status signal changes state, and the calibration value is stored into a calibration value register; a memory module, for receiving, storing and outputting the calibration value; and a reference signal generator, receiving the calibration value to provide the analog reference signal. The present invention can therefore be used to automatically calibrate a system with fewer external components to provide qualified systems. | 06-09-2011 |
Patent application number | Description | Published |
20100277100 | ELECTRONIC BALLAST WITH DIMMING CONTROL FROM POWER LINE SENSING - The present invention discloses an electronic ballast with dimming control from power line sensing for a fluorescent lamp, comprising: a line switching sensing circuit, used to generate a switching sensing signal by performing a voltage comparison operation on a DC voltage, and generate a reset signal according to the off time of the power line; a control voltage generator, used to generate a control voltage according to the count of said switching sensing signal; a voltage controlled oscillator, used to generate an oscillating signal according to the control voltage; and a non-overlapping driver, used to generate a high side driving signal and a low side driving signal according to the oscillating signal. | 11-04-2010 |
20100277101 | ELECTRONIC BALLAST WITH DIMMING CONTROL FROM POWER LINE SENSING - The present invention discloses an electronic ballast with dimming control from power line sensing for a fluorescent lamp, comprising: a line switching sensing circuit, used to generate a switching sensing signal by performing a voltage comparison operation on a DC voltage; an oscillating signal gating unit, used to gate an oscillating signal with a pulse signal to generate a gated oscillating signal, wherein the pulse width of the pulse signal is generated according to the switching sensing signal; and a non-overlapping driver, used to generate a high side driving signal and a low side driving signal according to the gated oscillating signal. | 11-04-2010 |
20100277102 | ELECTRONIC BALLAST WITH DIMMING CONTROL FROM POWER LINE SENSING - The present invention discloses an electronic ballast with dimming control from power line sensing for a fluorescent lamp, comprising: a line switching sensing circuit, used to generate a switching sensing signal by performing a voltage comparison operation on a DC voltage, and generate a reset signal according to the off time of the power line; a dimming voltage generator, used to generate a dimming voltage according to a count of the switching sensing signal; and a phase-controlled non-overlapping driver, used to generate a high side driving signal and a low side driving signal for delivering a lamp current according to the dimming voltage, wherein the dimming voltage is used to generate a phase, and the phase is used to generate the lamp current. | 11-04-2010 |
20110012536 | ELECTRONIC BALLAST WITH DIMMING CONTROL FROM POWER LINE SENSING - The present invention discloses an electronic ballast with dimming control from power line sensing for a fluorescent lamp, comprising: a control voltage generator, used to generate a control voltage according to a switching count of a power line; an oscillator, used to generate an oscillating signal, wherein the oscillating signal is of a fixed frequency and has a rising voltage portion and a falling voltage portion; and a comparator, used to generate a high side gating signal according to voltage comparison of the oscillating signal and the control voltage. | 01-20-2011 |
20110169425 | SINGLE CHIP BALLAST CONTROLLER FOR STEP-DIMMING OF A FLUORESCENT LAMP - The present invention relates a single chip ballast controller for step-dimming of a fluorescent lamp, comprising: a counting circuit, used to generate a switching count by counting the instances where the supply voltage falls below a threshold voltage; a reference voltage generator, used to generate a reference voltage proportional to the switching count; and a gating signal generator, used to generate a high side driving signal and a low side driving signal according to an error voltage between the reference voltage and a current sensing voltage to regulate the current sensing voltage at the reference voltage, wherein the current sensing voltage is proportional to a lamp current flowing through the fluorescent lamp. | 07-14-2011 |