Patent application number | Description | Published |
20090001431 | Method for forming semiconductor contacts - In one embodiment of the invention, contact patterning may be divided into two or more passes which may allow designers to control the gate height critical dimension relatively independent from the contact top critical dimension. | 01-01-2009 |
20090267175 | DOUBLE PATTERNING TECHNIQUES AND STRUCTURES - Double patterning techniques and structures are generally described. In one example, a method includes depositing a first photoresist to a semiconductor substrate, forming a first integrated circuit (IC) pattern in the first photoresist, the first IC pattern comprising one or more trench structures, protecting the first IC pattern in the first photoresist from actions that form a second IC pattern in a second photoresist, depositing the second photoresist to the first IC pattern, and forming the second IC pattern in the second photoresist, the second IC pattern comprising one or more structures that are sufficiently close to the one or more trench structures of the first IC pattern to cause scumming of the second photoresist in the one or more trench structures of the first IC pattern. | 10-29-2009 |
20100068633 | SUB-RESOLUTION ASSIST FEATURES - Systems and techniques relating to the layout and use of sub-resolution assist features. In one implementation, a mask includes a first feature and a second feature separated from each other by a gap and a sub-resolution assist feature bridging the gap between the first feature and the second feature. | 03-18-2010 |
20100171156 | Method for Forming Semiconductor Contacts - In one embodiment of the invention, contact patterning may be divided into two or more passes which may allow designers to control the gate height critical dimension relatively independent from the contact top critical dimension. | 07-08-2010 |
20110274882 | PATTERNED NANOWIRES - Nanowires suspended from a substrate surface and methods of making nanowires suspended from a substrate surface are provided. The suspended nanowires are comprised of a variety of materials, including metals and mixtures of metals. Suspended nanowires supply large surface areas for applications such as, for example, energy storage and catalysis. Embodiments of the invention provide three dimensional nanowires attached to a substrate surface and arrays of three dimensional nanowires. | 11-10-2011 |
20130216941 | LITHOGRAPHY MASK HAVING SUB-RESOLUTION PHASED ASSIST FEATURES - Techniques are disclosed for using sub-resolution phased assist features (SPAF) in a lithography mask to improve through process pattern fidelity and/or mitigate inverted aerial image problems. The technique also may be used to improve image contrast in non-inverted weak image sites. The use of SPAF in accordance with some such embodiments requires no adjustment to existing design rules, although adjustments can be made to enable compliance with mask inspection constraints. The use of SPAF also does not require changing existing fab or manufacturing processes, especially if such processes already comprehend phased shift mask capabilities. The SPAFs can be used to enhance aerial image contrast, without the SPAFs themselves printing. In addition, the SPAF phase etch depth can be optimized so as to make adjustments to a given predicted printed feature critical dimension. | 08-22-2013 |
20130320456 | GATE ALIGNED CONTACT AND METHOD TO FABRICATE SAME - Gate aligned contacts and methods of forming gate aligned contacts are described. For example, a method of fabricating a semiconductor structure includes forming a plurality of gate structures above an active region formed above a substrate. The gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contact plugs is formed, each contact plug formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts is formed, each contact formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. The plurality of contacts and the plurality of gate structures are formed subsequent to forming the plurality of contact plugs. | 12-05-2013 |
20140017899 | DOUBLE PATTERNING LITHOGRAPHY TECHNIQUES - Techniques are disclosed for double patterning of a lithographic feature using a barrier layer between the pattern layers. In some cases, the techniques may be implemented with double patterning of a one- or two-dimensional photolithographic feature, for example. In some embodiments, the barrier layer is deposited to protect a first photoresist pattern prior to application of a second photoresist pattern thereon and/or to tailor (e.g., shrink) one or more of the critical dimensions of a trench, hole, or other etchable geometric feature to be formed in a substrate or other suitable surface via lithographic processes. In some embodiments, the techniques may be implemented to generate/print small features (e.g., less than or equal to about 100 nm) including one- and two-dimensional features/structures of varying complexity. | 01-16-2014 |
20140073137 | METHODS FOR SINGLE EXPOSURE - SELF-ALIGNED DOUBLE, TRIPLE, AND QUADRUPLE PATTERNING - A method including forming a pattern on a surface of a substrate, the pattern including one of discrete structures including at least one sidewall defining an oblique angle relative to the surface and discrete structures complemented with a material layer therebetween, the material layer including a volume modified into distinct regions separated by at least one oblique angle relative to the surface; and defining circuit features on the substrate using the pattern, the features having a pitch less than a pitch of the pattern. | 03-13-2014 |
20140117488 | PATTERN DECOMPOSITION LITHOGRAPHY TECHNIQUES - Techniques are disclosed for realizing a two-dimensional target lithography feature/pattern by decomposing (splitting) it into multiple unidirectional target features that, when aggregated, substantially (e.g., fully) represent the original target feature without leaving an unrepresented remainder (e.g., a whole-number quantity of unidirectional target features). The unidirectional target features may he arbitrarily grouped such that, within a grouping, all unidirectional target features share a common target width value. Where multiple such groupings are provided, individual groupings may or may not have the same common target width value. In some cases, a series of reticles is provided, each reticle having a mask pattern correlating to a grouping of unidirectional target features. Exposure of a photoresist material via the aggregated series of reticles substantially (e.g., fully) produces the original target feature/pattern. The pattern decomposition techniques may be integrated into any number of patterning processes, such as litho-freeze-litho-etch and litho-etch-litho-etch patterning processes. | 05-01-2014 |
20140117489 | SUB-SECOND ANNEALING LITHOGRAPHY TECHNIQUES - Techniques are disclosed for sub-second annealing a lithographic feature to, for example, tailor or otherwise selectively alter its profile in one, two, or three dimensions. Alternatively, or in addition to, the techniques can be used, for example, to smooth or otherwise reduce photoresist line width/edge roughness and/or to reduce defect density. In some cases, the sub-second annealing process has a time-temperature profile that can effectively change the magnitude of resist shrinkage in one or more dimensions or otherwise modify the resist in a desired way (e.g., smooth the resist). The techniques may be implemented, for example, with any type of photoresist (e.g., organic, inorganic, hybrid, molecular photoresist materials) and can be used in forming, for instance, processor microarchitectures, memory circuitry, logic arrays, and numerous other digital/analog/hybrid integrated semiconductor devices. | 05-01-2014 |
20140272711 | PRE-PATTERNED HARD MASK FOR ULTRAFAST LITHOGRAPHIC IMAGING - A method of fabricating a substrate including coating a first resist onto a hardmask, exposing regions of the first resist to electromagnetic radiation at a dose of 10.0 mJ/cm | 09-18-2014 |
Patent application number | Description | Published |
20100083018 | FAN SPEED CONTROL OF SILICON BASED DEVICES IN LOW POWER MODE TO REDUCE PLATFORM POWER - In general, in one aspect, the disclosure describes running a cooling fan within a computer at low speed while the computer is in low temperature operations (e.g., idle). The operation of the cooling fan may reduce processor (CPU) temperature enough to decrease processor leakage power, offsetting the power consumption of the fan, and possibly resulting in a net system power reduction. The benefit at the platform level increases further when considering the low efficiency of voltage regulation (VR) in this lower power regime, and potentially reductions in other components (e.g., graphics processor). The optimal fan speed is the speed at which the overall system power is reduced the most (e.g., processor power savings is greater than fan power utilized). The optimal temperature may be determined dynamically during operation or may be determined in manufacturing and applied statically during operation. | 04-01-2010 |
20120185711 | FAN CONTROL DURING LOW TEMPERATURE OPERATIONS TO REDUCE PLATFORM POWER - In general, in one aspect, the disclosure describes running a cooling fan within a computer at low speed while the computer is in low temperature operations (e.g., idle). The operation of the cooling fan may reduce CPU temperature enough to decrease CPU leakage power, offsetting the power consumption of the fan, and possibly resulting in a net system power reduction. The benefit at the platform level increases further when considering the low efficiency of voltage regulation (VR) in this lower power regime, and potentially reductions in other components (e.g., graphics processor). The optimal fan speed is the speed at which the overall system power is reduced the most (e.g., CPU power savings is greater than fan power utilized). The optimal temperature may be determined dynamically during operation or may be determined in manufacturing and applied statically during operation. | 07-19-2012 |