Patent application number | Description | Published |
20110214129 | MANAGEMENT OF MULTIPLE RESOURCE PROVIDERS - A device receives a request for an amount of a resource. It determines for each resource provider in a set of resource providers a current load, a requested load corresponding to the requested amount of the resource, and an additional load corresponding to an expected state of an application. It determines for each of the resource providers an expected total load on the basis of the current load, the requested load, and the additional load. It subsequently selects from the set of resource providers a preferred resource provider on the basis of the expected total loads. The resource may be one of the following: memory, processing time, data throughput, power, and usage of a device. | 09-01-2011 |
20110317802 | CLOCK GLITCH DETECTION CIRCUIT - In a first circuit for detecting clock glitches in a clock signal, a master counter is clocked by the clock signal and memorizes a master count. An incrementer advances the master count by one increment. A slave counter is clocked by the clock signal and memorizes a slave count. The slave count is retarded relative to the master count by at least clock edges. A comparator determines whether the difference between the master count and the slave count is at least. In a related aspect, a synchronous circuit comprises a clock tree for transmitting a clock signal from a start point to one or more other points, the start point and the other points comprising a first point and second point. A first counter is clocked by the clock signal at the first point and memorizes a first count. A first incrementer advances the first count by one increment. A second counter is clocked by the clock signal at the second point and memorizes a second count. A second incrementer advances the second count by one increment. A comparator determines the difference between the first count and the second count, or determines whether the first count and the second count differ. The synchronous circuit may comprise the first circuit. A second circuit for detecting clock glitches in a clock signal is also provided. The second circuit is intended to be integrated in the synchronous circuit. | 12-29-2011 |
20130054988 | INTEGRATED CIRCUIT DEVICE, SIGNAL PROCESSING SYSTEM AND METHOD FOR MANAGING POWER RESOURCES OF A SIGNAL PROCESSING SYSTEM - An integrated circuit device comprises a power resource management module for managing at least one power resource of a signal processing system. The power resource management module comprises an input for receiving an indication of an intended state change for the signal processing system. The power resource management module is arranged to calculate at least one power resource load prediction for implementing the indicated system state change in response to receiving the indication of an intended state change. The power resource management module comprises an output connectable to the at least one power resource of the signal processing system for configuring the at least one power resource to fulfill the at least one power resource load prediction. | 02-28-2013 |
20140006841 | CLOCK GLITCH DETECTION CIRCUIT | 01-02-2014 |
20140173247 | PROCESSING APPARATUS AND METHOD OF SYNCHRONIZING A FIRST PROCESSING UNIT AND A SECOND PROCESSING UNIT - A processing apparatus, comprising at least a first processing unit and a second processing unit, is proposed. The first processing unit comprises a set of first stateful elements, the second processing unit comprises a set of second stateful elements. A set of synchronization data lines may connect the first stateful elements to the second stateful elements in a pairwise manner. A control unit may control the first processing unit, the second processing unit and the synchronization data lines so as to copy the states of the first stateful elements in parallel via the synchronization data lines to the second stateful elements in response to a synchronization request. A method of synchronizing the processing units is also proposed. | 06-19-2014 |
20150178102 | SYSTEM-ON-CHIP, METHOD OF MANUFACTURE THEREOF AND METHOD OF CONTROLLING A SYSTEM-ON-CHIP - A system-on-chip comprises a plurality of functional domains. The plurality of functional domains comprise a first domain and a second domain, the first domain having a first active mode of operation and the second domain having a second active mode of operation different from the first active mode of operation. The system-on-chip also comprises a control unit operably coupled to the first and second domains and capable of placing the first domain in the first active mode and the second domain in the second active mode so that the first domain is in the first active mode and the second domain is in the second active mode substantially contemporaneously. The first active mode of operation is functionally different from the second active mode of operation. | 06-25-2015 |
20150370580 | CONFIGURATION CONTROLLER FOR AND A METHOD OF CONTROLLING A CONFIGURATION OF A CIRCUITRY - A configuration controller for and a method of controlling a configuration of a circuitry are provided. The configuration controller comprises an input, a selection checker, a data selector and an output. The input receives an input configuration selection signal which is encoded according to a specific encoding scheme. The selection checker checks a correctness of the received input configuration selection signal and provides to the data selector a selection signal which indicates a specific configuration selection if the input configuration selection data is correct or indicates a default configuration selection if the input configuration selection signal is incorrect according to the specific encoding scheme. The data selector selects configuration data from its internal configuration data storage in accordance with the selection signal and provides the selected configuration data to the output. | 12-24-2015 |
20160124800 | MICROCONTROLLER UNIT AND METHOD OF OPERATING A MICROCONTROLLER UNIT - A microcontroller unit (MCU) having a functional state, a reset state, and one or more assertable fault sources is described. Each fault source has its own fault source assertion count and its own fault source assertion limit; the MCU is arranged to perform the following sequence of operations in a cyclic manner: if one or more of the fault sources are asserted, pass from the functional state to the reset state and increase the respective fault source assertion counts by one increment; if one or more of the fault source assertion counts exceeds the respective fault source assertion limit, disable the respective fault source; and pass from the reset state to the functional state. A method of operating an MCU is also disclosed. | 05-05-2016 |