Patent application number | Description | Published |
20090129481 | SYSTEM AND METHOD FOR TRANSCODING ENTROPY-CODED BITSTREAMS - A system and method for transcoding an entropy-coded bitstream is presented herein. The syntax elements of the entropy-coded bitstream are decoded and transcoded into a second format. The second format can comprise a simpler format for decoding. The foregoing advantageously alleviates the processing requirements for the video decompression engine. | 05-21-2009 |
20090257512 | Error Concealment for MPEG Decoding with Personal Video Recording Functionality - Error concealment for motion picture expert group (MPEG) decoding with personal video recording functionality. Error concealment of MPEG data may take place within various components within playback, recording, reading and writing data systems. The error concealment may be provided within existing systems whose components may not be capable of accommodating errors within MPEG data. In certain embodiments, the available data that contain no errors is maximized to conceal those portions of the data that do include errors. Various layers may be accommodated while performing error concealment, including the MPEG transport stream layer, the video layer, and the audio layer. | 10-15-2009 |
20100103195 | VIDEO, AUDIO AND GRAPHICS DECODE, COMPOSITE AND DISPLAY SYSTEM - A video, audio and graphics system uses multiple transport processors to receive in-band and out-of-band MPEG Transport streams, to perform PID and section filtering as well as DVB and DES decryption and to de-multiplex them. The system processes the PES into digital audio, MPEG video and message data. The system is capable of decoding multiple MPEG SLICEs concurrently. Graphics windows are blended in parallel, and blended with video using alpha blending. During graphics processing, a single-port SRAM is used equivalently as a dual-port SRAM. The video may include both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The system has a reduced memory mode in which video images are reduced in half in horizontal direction only during decoding. The system is capable of receiving and processing digital audio signals such as MPEG Layer 1 and Layer 2 audio and Dolby AC-3 audio, as well as PCM audio signals. The system includes a memory controller. The system includes a system bridge controller to interface a CPU with devices internal to the system as well as peripheral devices including PCI devices and I/O devices such as RAM, ROM and flash memory devices. The system is capable of displaying video and graphics in both the high definition (HD) mode and the standard definition (SD) mode. The system may output an HDTV video while converting the HDTV video and providing as another output having an SDTV format or another HDTV format. | 04-29-2010 |
20110122941 | VIDEO DECODING SYSTEM SUPPORTING MULTIPLE STANDARDS - System and method for decoding digital video data. The decoding system employs hardware accelerators that assist a core processor in performing selected decoding tasks. The hardware accelerators are configurable to support a plurality of existing and future encoding/decoding formats. The accelerators are configurable to support substantially any existing or future encoding/decoding formats that fall into the general class of DCT-based, entropy decoded, block-motion-compensated compression algorithms. The hardware accelerators illustratively comprise a programmable entropy decoder, an inverse quantization module, a inverse discrete cosine transform module, a pixel filter, a motion compensation module and a de-blocking filter. The hardware accelerators function in a decoding pipeline wherein at any given stage in the pipeline, while a given function is being performed on a given macroblock, the next macroblock in the data stream is being worked on by the previous function in the pipeline. | 05-26-2011 |
20120020412 | Method of Operating a Video Decoding System - A system and method for decoding a digital video data stream. In one aspect, a plurality of hardware acceleration modules are used together with a core processor. The accelerators operate in a decoding pipeline wherein, in any given stage, each accelerator operates on a particular macroblock of video data. In the subsequent pipeline stage, each accelerator works on the next macroblock in the data stream, which was worked on by another one of the accelerators in the previous stage. The core processor polls all of the accelerators during each stage. When all accelerators finish their tasks for a given stage, the core processor initiates the next stage. In another aspect, two variable-length decoders are employed to simultaneously decode two macroblock rows of a video frame. Each variable-length decoder works to decode an assigned row and the rows are variable-length decoded in parallel. The variable-length decoders operate as part of a pipeline wherein the variable-length decoders alternate, stage-by-stage, decoding macroblocks. | 01-26-2012 |
20120087593 | Inverse Quantizer Supporting Multiple Decoding Processes - The present invention provides an apparatus for performing inverse quantization for multiple decoding standards, where the functional operations that comprise the inverse quantizer are modularly implemented and can be selectably performed. Each operation can be represented via a table entry in an associated memory area, with the functional operation being performed via reference to that table entry. Functional operations can be bypassed as needed if inverse quantization does not need to be performed on a set of data. Certain other processing operations can be performed between steps as needed to accommodate different coding standards. Macroblock data can be read from and written back to a common storage area, or a direct path is provided for writing the data directly to a subsequent inverse transform device. | 04-12-2012 |
20120328000 | Video Decoding System Supporting Multiple Standards - System and method for decoding digital video data. The decoding system employs hardware accelerators that assist a core processor in performing selected decoding tasks. The hardware accelerators are configurable to support a plurality of existing and future encoding/decoding formats. The accelerators are configurable to support substantially any existing or future encoding/decoding formats that fall into the general class of DCT-based, entropy decoded, block-motion-compensated compression algorithms. The hardware accelerators illustratively comprise a programmable entropy decoder, an inverse quantization module, a inverse discrete cosine transform module, a pixel filter, a motion compensation module and a de-blocking filter. The hardware accelerators function in a decoding pipeline wherein at any given stage in the pipeline, while a given function is being performed on a given macroblock, the next macroblock in the data stream is being worked on by the previous function in the pipeline. | 12-27-2012 |
20130022105 | Video Decoding System Supporting Multiple Standards - System and method for decoding digital video data. The decoding system employs hardware accelerators that assist a core processor in performing selected decoding tasks. The hardware accelerators are configurable to support a plurality of existing and future encoding/decoding formats. The accelerators are configurable to support substantially any existing or future encoding/decoding formats that fall into the general class of DCT-based, entropy decoded, block-motion-compensated compression algorithms. The hardware accelerators illustratively comprise a programmable entropy decoder, an inverse quantization module, a inverse discrete cosine transform module, a pixel filter, a motion compensation module and a de-blocking filter. The hardware accelerators function in a decoding pipeline wherein at any given stage in the pipeline, while a given function is being performed on a given macroblock, the next macroblock in the data stream is being worked on by the previous function in the pipeline. | 01-24-2013 |
20130272433 | ERROR CONCEALMENT FOR MPEG DECODING WITH PERSONAL VIDEO RECORDING FUNCTIONALITY - Error concealment for motion picture expert group (MPEG) decoding with personal video recording functionality. Error concealment of MPEG data may take place within various components within playback, recording, reading and writing data systems. The error concealment may be provided within existing systems whose components may not be capable of accommodating errors within MPEG data. In certain embodiments, the available data that contain no errors is maximized to conceal those portions of the data that do include errors. | 10-17-2013 |