Patent application number | Description | Published |
20080299750 | MULTIPLE MILLISECOND ANNEALS FOR SEMICONDUCTOR DEVICE FABRICATION - A method of forming a doped region includes, in one embodiment, implanting a dopant into a region in a semiconductor substrate, recrystallizing the region by performing a first millisecond anneal, wherein the first millisecond anneal has a first temperature and a first dwell time, and activating the region using as second millisecond anneal after recrystallizing the region, wherein the second millisecond anneal has a second temperature and a second dwell time. In one embodiment, the first millisecond anneal and the second millisecond anneal use a laser. In one embodiment, the first temperature is the same as the second temperature and the first dwell time is the same as the second dwell time. In another embodiment, the first temperature is different from the second temperature and the first dwell time is different from the second dwell time. | 12-04-2008 |
20090026554 | SOURCE/DRAIN STRESSORS FORMED USING IN-SITU EPITAXIAL GROWTH - A method for forming a semiconductor device is provided. The method includes forming a semiconductor layer. The method further includes forming a gate structure overlying the semiconductor layer. The method further includes forming a high-k sidewall spacer adjacent to the gate structure. The method further includes forming a recess in the semiconductor layer, the recess aligned to the high-k sidewall spacer. The method further includes forming an in-situ doped epitaxial material in the recess, the epitaxial material having a natural lattice constant different from a lattice constant of the semiconductor layer to create stress in a channel region of the semiconductor device. | 01-29-2009 |
20090039420 | FINFET MEMORY CELL HAVING A FLOATING GATE AND METHOD THEREFOR - A fin field effect transistor (FinFET) memory cell and method of formation has a substrate for providing mechanical support. A first dielectric layer overlies the substrate. A fin structure overlies the dielectric layer and has a first current electrode and a second current electrode separated by a channel. A floating gate has a vertical portion that is adjacent to and electrically insulated from a side of the channel and has a horizontal portion overlying the first dielectric layer and extending laterally away from the channel. The floating gate stores electrical charge. A second dielectric layer is adjacent the floating gate. A control gate adjacent the second dielectric layer and physically separated from the floating gate by the second dielectric layer. The “L-shape” of the floating gate enhances capacitive coupling ratio between the control gate and the floating gate. | 02-12-2009 |
20090321879 | SILICIDED BASE STRUCTURE FOR HIGH FREQUENCY TRANSISTORS - High frequency performance of (e.g., silicon) bipolar devices ( | 12-31-2009 |
20100059859 | VARACTOR STRUCTURE AND METHOD - An improved varactor diode ( | 03-11-2010 |
20100059860 | COUNTER-DOPED VARACTOR STRUCTURE AND METHOD - An improved varactor diode ( | 03-11-2010 |
20100314664 | SILICIDED BASE STRUCTURE FOR HIGH FREQUENCY TRANSISTORS - High frequency performance of (e.g., silicon) bipolar devices is improved by reducing the extrinsic base resistance Rbx. Emitter, base and collector regions are formed in or on a semiconductor substrate. The emitter contact has a portion that overhangs a portion of the extrinsic base contact, thereby forming a cave-like cavity between the overhanging portion of the emitter contact and the underlying regions of the extrinsic base contact. When the emitter contact and the extrinsic base contact are silicided, some of the metal atoms forming the silicide penetrate into the cavity so that the highly conductive silicided extrinsic base contact extends under the edge of the emitter contact closer to the base itself, thereby reducing Rbx. Smaller Rbx provides transistors with higher f | 12-16-2010 |
20100329043 | Two-Transistor Floating-Body Dynamic Memory Cell - Embodiments relate to a two-transistor (2T) floating-body cell (FBC) for embedded-DRAM applications. Further embodiments pertain to a floating-body/gate cell (FBGC), which yields reduction in power dissipation, in addition to better signal margin, longer data retention, and higher memory density. | 12-30-2010 |
20110031588 | VARACTOR STRUCTURE AND METHOD - An improved varactor diode ( | 02-10-2011 |
20110140240 | VARACTOR DIODES - An improved varactor diode is obtained by providing a substrate having a first surface and in which are formed a first N region having a first peak dopant concentration located at a first depth beneath the surface, and a first P region having a second peak dopant concentration greater than the first peak dopant concentration located at a second depth beneath the surface less than the first depth, and a second P region having a third peak dopant concentration greater than the second peak dopant concentration and located at a third depth at or beneath the surface less than the second depth, so that the first P region provides a retrograde doping profile whose impurity concentration increases with distance from the inward edge of the second P region up to the second peak dopant concentration. | 06-16-2011 |
20110210430 | DEVICE WITH GROUND PLANE FOR HIGH FREQUENCY SIGNAL TRANSMISSION AND METHOD THEREFOR - A method for forming a semiconductor structure includes forming an isolation region in a semiconductor substrate; forming a conductive layer over the isolation region; forming a first dielectric layer over the conductive layer; forming a plurality of conductive vias extending through the first dielectric layer to the conductive layer and electrically contacting the conductive layer; forming a second dielectric layer over the first dielectric layer; and forming a conductive ground plane in the second dielectric layer. Each of the plurality of conductive vias is in electrical contact with the conductive ground plane, and the conductive ground plane includes an opening, wherein the opening is located directly over the conductive layer. At least one interconnect layer may be formed over the second dielectric layer and may include a transmission line which transmits a signal having a frequency of at least 30 gigahertz. | 09-01-2011 |
20110263112 | METHOD FOR FORMING A SCHOTTKY DIODE HAVING A METAL-SEMICONDUCTOR SCHOTTKY CONTACT - A method for forming a metal-semiconductor Schottky contact in a well region is provided. The method includes forming a first insulating layer overlying a shallow trench isolation in the well region; and removing a portion of the first insulating layer such that only the well region and a portion of the shallow trench isolation is covered by a remaining portion of the first insulating layer. The method further includes forming a second insulating layer overlying the remaining portion of the first insulating layer and using a contact mask, forming a contact opening in the second insulating layer and the remaining portion of the first insulating layer to expose a portion of the well region. The method further includes forming the metal-semiconductor Schottky contact in the exposed portion of the well region by forming a metal layer in the contact opening and annealing the metal layer. | 10-27-2011 |
20110267149 | SWITCHED CAPACITOR CIRCUIT FOR A VOLTAGE CONTROLLED OSCILLATOR - A switched capacitor circuit for use at at least one operating frequency is provided. The switched capacitor may include an inductive element having a first terminal coupled to a switching voltage and a second terminal. The switched capacitor circuit may further include a hetero-junction bipolar transistor (HBT) having a base terminal coupled to the second terminal of the inductive element, a first conducting terminal, and a second conducting terminal coupled to a voltage supply terminal. The switched capacitor circuit may further include a capacitor having a first terminal coupled to the first conducting terminal of the HBT and a second terminal coupled to a node, wherein a capacitance value at the node is a function of the switching voltage, and wherein the inductive element is configured such that a combined impedance of an impedance of the capacitor, an impedance of the HBT, and an impedance of inductive element resonates at the at least one operating frequency only when the HBT is substantially non-conducting. | 11-03-2011 |
20120021586 | METHODS FOR FORMING VARACTOR DIODES - Methods are disclosed for forming an improved varactor diode having first and second terminals. The methods include providing a substrate having a first surface in which are formed isolation regions separating first and second parts of the diode. A varactor junction is formed in the first part with a first side coupled to the first terminal and a second side coupled to the second terminal via a sub-isolation buried layer (SIBL) region extending under the bottom and partly up the sides of the isolation regions to a further doped region that is ohmically connected to the second terminal. The first part does not extend to the SIBL region. The varactor junction desirably comprises a hyper-abrupt doped region. The combination provides improved tuning ratio, operating frequency and breakdown voltage of the varactor diode while still providing adequate Q. | 01-26-2012 |
20120080804 | ELECTRONIC DEVICE INCLUDING INTERCONNECTS WITH A CAVITY THEREBETWEEN AND A PROCESS OF FORMING THE SAME - A process of forming an electronic device can include providing a first interconnect over a substrate having a primary surface, depositing a first insulating layer over the first interconnect, and patterning the first insulating layer to define an opening extending towards the first interconnect. The process can also include depositing a second insulating layer over the first insulating layer to seal the opening and form a cavity within the first opening, and forming a second interconnect over the first and second insulating layers. The cavity can be disposed between the first interconnect and the second interconnect. In another aspect, an electronic device can include a first interconnect, a first insulating layer defining a cavity, and a second interconnect. The cavity can be disposed between the first interconnect and the second interconnect, and a via may not be exposed within the cavity. | 04-05-2012 |
20120199881 | BIPOLAR TRANSISTOR AND METHOD WITH RECESSED BASE ELECTRODE - High frequency performance of (e.g., silicon) bipolar devices ( | 08-09-2012 |
20120235757 | VOLTAGE-CONTROLLED OSCILLATORS AND RELATED SYSTEMS - Apparatus are provided for voltage-controlled oscillators (VCOs) and related systems. An exemplary VCO includes an active-circuit arrangement employing cross-coupled amplifying elements that facilitate generation of an oscillating signal, plus a resonator arrangement capacitively coupled via resonator terminals to primary terminals of the active-circuit arrangement, to influence an oscillation frequency of the oscillating signal based on a difference between control voltages applied to first and second control terminals of the resonator arrangement. When employing bipolar amplifying elements their control terminals are cross-coupled to the opposing resonator terminals. VCO output may be taken from the primary terminals or from the resonator terminals. | 09-20-2012 |
20120235758 | VOLTAGE-CONTROLLED OSCILLATORS AND RELATED SYSTEMS - Apparatus are provided for voltage-controlled oscillators and related systems. An exemplary voltage-controlled oscillator includes an active-circuit arrangement that facilitates generation of an oscillating signal, and a resonator arrangement capacitively coupled to the active-circuit arrangement to influence an oscillation frequency of the oscillating signal based on a difference between a first control voltage and a second control voltage. | 09-20-2012 |
20120319787 | VOLTAGE CONTROLLED OSCILLATOR HAVING A RESONATOR CIRCUIT WITH A PHASE NOISE FILTER - An oscillator circuit is provided for generating an oscillating signal. The oscillator circuit includes a transistor circuit, a resonator circuit, and first and second transmission line open stubs. The transistor circuit is coupled to a first node and a second node of the oscillator circuit. The transistor circuit is for facilitating oscillation of the oscillating signal. The resonator circuit is coupled to the first node and the second node, and includes an inductance and a capacitance. The first and second transmission line open stubs are coupled to the first and second nodes, respectively. The first and second transmission line open stubs have a length substantially equal to a quarter wavelength of a second harmonic of the oscillating signal, and are for removing the second harmonic from the oscillating signal. In another embodiment, first and second half wave AC shorted stubs are used to remove the second harmonic from the oscillating signal. | 12-20-2012 |
20130082790 | VOLTAGE-CONTROLLED OSCILLATORS AND RELATED SYSTEMS - Apparatus are provided for voltage-controlled oscillators and related systems. An exemplary voltage-controlled oscillator includes a first variable capacitance element, a second variable capacitance element coupled between the first control voltage node and the third node, and an inductive element coupled between the variable capacitance elements to provide an inductance between the variable capacitance elements at an oscillation frequency of an oscillating signal at an output node. The first variable capacitance element is coupled between a first control voltage node and the output node, the second variable capacitance element is coupled to the first control voltage node, and a second inductive element is coupled between the second variable capacitance element and a second control voltage node. | 04-04-2013 |
20140001650 | ELECTRONIC DEVICE INCLUDING INTERCONNECTS WITH A CAVITY THEREBETWEEN AND A PROCESS OF FORMING THE SAME | 01-02-2014 |
20140027817 | HYBRID TRANSISTOR - A hybrid transistor ( | 01-30-2014 |
20140131772 | SEMICONDUCTOR DEVICES WITH RECESSED BASE ELECTRODE - High frequency performance of (e.g., silicon) bipolar devices is improved by reducing the extrinsic base resistance Rbx. An emitter, an intrinsic base, and a collector are formed in a semiconductor body. An emitter contact has a region that overlaps a portion of an extrinsic base contact. A sidewall is formed in the extrinsic base contact proximate a lateral edge of the overlap region of the emitter contact. The sidewall is amorphized during or after formation so that when the emitter contact and the extrinsic base contact are, e.g., silicided, some of the metal atoms forming the silicide penetrate into the sidewall so that part of the highly conductive silicided extrinsic base contact extends under the edge of the overlap region of the emitter contact closer to the intrinsic base, thereby reducing Rbx. Smaller Rbx provides transistors with higher f | 05-15-2014 |
20150056767 | METHODS FOR FORMING TRANSISTORS - A hybrid transistor is produced to have a substrate with a first (e.g., P type) well region and a second (e.g., N type) well region with an NP or PN junction therebetween. A MOS portion of the hybrid transistor has an (e.g., N type) source region in the first well region and a gate conductor overlying and insulated from the well regions. A drain or anode (D/A) portion in the second well region collects current from the source region, and includes a bipolar transistor having an (e.g., N+) emitter region, a (e.g., P type) base region and a (e.g., N type) collector region laterally separated from the junction. Different LDMOS-like or IGBT-like properties are obtained depending on whether the current is extracted from the hybrid transistor via the bipolar transistor base or emitter or both. The bipolar transistor is desirably a vertical hetero-junction transistor. | 02-26-2015 |