Patent application number | Description | Published |
20090085210 | STRUCTURES AND METHODS FOR REDUCTION OF PARASITIC CAPACITANCES IN SEMICONDUCTOR INTEGRATED CIRCUITS - A semiconductor structure and a method for forming the same. The structure includes (a) a substrate which includes semiconductor devices and (b) a first ILD (inter-level dielectric) layer on top of the substrate. The structure further includes N first actual metal lines in the first ILD layer, N being a positive integer. The N first actual metal lines are electrically connected to the semiconductor devices. The structure further includes first trenches in the first ILD layer. The first trenches are not completely filled with solid materials. If the first trenches are completely filled with first dummy metal lines, then (i) the first dummy metal lines are not electrically connected to any semiconductor device and (ii) the N first actual metal lines and the first dummy metal lines provide an essentially uniform pattern density of metal lines across the first ILD layer. | 04-02-2009 |
20090159948 | TRENCH METAL-INSULATOR METAL (MIM) CAPACITORS - The present invention relates to a semiconductor device that contains a trench metal-insulator-metal (MIM) capacitor and a field effect transistor (FET), and a design structure including the semiconductor device embodied in a machine readable medium. The trench MIM capacitor comprises a first metallic electrode layer located over interior walls of a trench in a substrate, a dielectric layer located in the trench over the first metallic electrode layer, and a second metallic electrode layer located in the trench over the dielectric layer. The FET comprises a source region, a drain region, a channel region between the source and drain regions, and a gate electrode over the channel region. The trench MIM capacitor is connected to the FET by a metallic strap. The semiconductor device of the present invention can be fabricated by a process in which the trench MIM capacitor is formed after the FET source/drain region but before the FET source/drain metal silicide contacts, for minimizing metal contamination in the FET. | 06-25-2009 |
20100210098 | SELF-ALIGNED CONTACT - A method of forming contacts for semiconductor devices, the method including depositing an inter-level dielectric (ILD) over a plurality of gate stacks, in which the divots within the inter-level dielectric layer are defined by the spaces between the gate stacks, filling the divots with an initial fill material, depositing a masking material on the dielectric over the gate stacks, and selectively etching the fill material to form contact vias. The fill material may be a self-assembly material such as a multi-block copolymer in which the blocks self organize vertically within the divots, so that a selective etch of the block material will remove the vertically organized blocks from the divot, but leave at least one block over the gate regions. In another embodiment, the fill material may be a metal, and the masking material may be a parylene based polymer. | 08-19-2010 |
20130113068 | LOW-K DIELECTRIC PROTECTION SPACER FOR PATTERNING THROUGH SUBSTRATE VIAS THROUGH A LOW-K WIRING LAYER - A low-K value dielectric protection spacer for patterning through substrate vias (TSVs) through a low-K value wiring layer. A method for forming a low-K value dielectric protection spacer includes etching a via opening through a low-K value dielectric interconnect layer. A protective layer is deposited in the via opening and on the low-K value dielectric interconnect layer. At least a portion of the protective layer is etched from the bottom of the via opening and from a horizontal surface of the low-K value dielectric interconnect layer. The etching leaving a protective sidewall spacer on a sidewall of the via opening. A through substrate via is etched through the bottom of the via opening and through the semiconductor substrate. The through substrate via is filled with a conductive material. | 05-09-2013 |
20130181330 | INTEGRATING THROUGH SUBSTRATE VIAS INTO MIDDLE-OF-LINE LAYERS OF INTEGRATED CIRCUITS - A semiconductor wafer has an integrated, through substrate, via (TSV). The semiconductor wafer includes a substrate. A dielectric layer may be formed on a first side of the substrate. A through substrate via may extend through the dielectric layer and the substrate. The through substrate via may include a conductive material and an isolation layer. The isolation layer may at least partially surround the conductive material. The isolation layer may have a tapered portion. | 07-18-2013 |
20130221494 | STRUCTURE AND METHOD FOR STRAIN-RELIEVED TSV - A semiconductor die including strain relief for through substrate vias (TSVs). The semiconductor die includes a semiconductor substrate having an active face. The semiconductor substrate includes conductive layers connected to the active face, The semiconductor die also includes a through substrate via extending only through the substrate. The through substrate via may include a substantially constant diameter through a length of the through substrate via. The through substrate via may be filled with a conductive filler material. The semiconductor die also includes an isolation layer surrounding the through substrate via. The isolation layer may include two portions: a recessed portion near the active face of the substrate capable of relieving stress from the conductive filler material, and a dielectric portion. A composition of the recessed portion may differ from the dielectric portion. | 08-29-2013 |
20140252561 | VIA-ENABLED PACKAGE-ON-PACKAGE - A via-enabled package-on-package circuit includes a first package including a first package die having a plurality of through substrate vias (TSVs). The TSVs are configured to carry the input/output signaling for at least one second package die. | 09-11-2014 |
20140266286 | THROUGH-SUBSTRATE VIA WITH A FUSE STRUCTURE - A device includes a conductive via to provide an electrical path through a substrate. The device further includes a conductive element. The device further includes a fuse coupled to the conductive via and coupled to the conductive element to provide a conductive path between the conductive via and the conductive element. The conductive path enables testing of continuity of at least a portion of the conductive via. The fuse is configured to be disabled after the testing of the continuity of the conductive via. | 09-18-2014 |
20140302674 | METHOD FOR STRAIN-RELIEVED THROUGH SUBSTRATE VIAS - A semiconductor die including strain relief for through substrate vias (TSVs). A method for strain relief of TSVs includes defining a through substrate via cavity in a substrate. The method also includes depositing an isolation layer in the cavity. The method further includes filling the cavity with a conductive material. The method also includes removing a portion of the isolation layer to create a recessed portion. | 10-09-2014 |
20140327105 | ELECTROSTATIC DISCHARGE DIODE - A method includes thinning a back-side of a substrate to expose a portion of a first via that is formed in the substrate. The method also includes forming a first diode at the back-side of the substrate. The first diode is coupled to the first via. | 11-06-2014 |
20150048465 | SMALL FORM FACTOR MAGNETIC SHIELD FOR MAGNETORESTRICTIVE RANDOM ACCESS MEMORY (MRAM) - Some implementations provide a die that includes a magnetoresistive random access memory (MRAM) cell array that includes several MRAM cells. The die also includes a first ferromagnetic layer positioned above the MRAM cell array, a second ferromagnetic layer positioned below the MRAM cell array, and several vias positioned around at least one MRAM cell. The via comprising a ferromagnetic material. In some implementations, the first ferromagnetic layer, the second ferromagnetic layer and the several vias define a magnetic shield for the MRAM cell array. The MRAM cell may include a magnetic tunnel junction (MTJ). In some implementations, the several vias traverse at least a metal layer and a dielectric layer of the die. In some implementations, the vias are through substrate vias. In some implementations, the ferromagnetic material has high permeability and high B saturation. | 02-19-2015 |