Patent application number | Description | Published |
20110163449 | SUPERFILLED METAL CONTACT VIAS FOR SEMICONDUCTOR DEVICES - In accordance with one aspect of the invention, a method is provided for fabricating a semiconductor element having a contact via. In such method, a hole can be formed in a dielectric layer to at least partially expose a region including at least one of semiconductor or conductive material. A seed layer can be deposited over a major surface of the dielectric layer and over a surface within the hole. In one embodiment, the seed layer can include a metal selected from the group consisting of iridium, osmium, palladium, platinum, rhodium, and ruthenium. A layer consisting essentially of cobalt can be electroplated over the seed layer within the hole to form a contact via in electrically conductive communication with the region. | 07-07-2011 |
20110233513 | ENHANCED BONDING INTERFACES ON CARBON-BASED MATERIALS FOR NANOELECTRONIC DEVICES - Semiconductor structures and electronic devices are provided that includes at least one layer of an interfacial dielectric material located on an upper surface of a carbon-based material. The at least one layer of interfacial dielectric material has a short-range crystallographic bonding structure, typically hexagonal, that is the same as that of the carbon-based material and, as such, the at least one layer of interfacial dielectric material does not change the electronic structure of the carbon-based material. The presence of the at least one layer of interfacial dielectric material having the same short-range crystallographic bonding structure as that of the carbon-based material improves the interfacial bonding between the carbon-based material and any overlying material layer, including a dielectric material, a conductive material or a combination of a dielectric material and a conductive material. The improved interfacial bonding in turn facilitates formation of devices including a carbon-based material. | 09-29-2011 |
20130140681 | SUPERFILLED METAL CONTACT VIAS FOR SEMICONDUCTOR DEVICES - In accordance with one aspect of the invention, a method is provided for fabricating a semiconductor element having a contact via. In such method, a hole can be formed in a dielectric layer to at least partially expose a region including at least one of semiconductor or conductive material. A seed layer can be deposited over a major surface of the dielectric layer and over a surface within the hole. In one embodiment, the seed layer can include a metal selected from the group consisting of iridium, osmium, palladium, platinum, rhodium, and ruthenium. A layer consisting essentially of cobalt can be electroplated over the seed layer within the hole to form a contact via in electrically conductive communication with the region. | 06-06-2013 |
20130320544 | CORROSION/ETCHING PROTECTION IN INTEGRATION CIRCUIT FABRICATIONS - A method of producing reduced corrosion interconnect structures and structures thereby formed. A method of producing microelectronic interconnects having reduced corrosion begins with a damascene structure having a first dielectric and a first interconnect. A metal oxide layer is deposited selectively to metal or nonselective over the damascene structure and then thermally treated. The treatment converts the metal oxide over the first dielectric to a metal silicate while the metal oxide over the first interconnect remains as a self-aligned protective layer. When a subsequent dielectric stack is formed and patterned, the protective layer acts as an etch stop, oxidation barrier and ion bombardment protector. The protective layer is then removed from the patterned opening and a second interconnect formed. In a preferred embodiment the metal oxide is a manganese oxide and the metal silicate is a MnSiCOH, the interconnects are substantially copper and the dielectric contains ultra low-k. | 12-05-2013 |
20130328174 | Edge Protection of Bonded Wafers During Wafer Thinning - A method of edge protecting bonded semiconductor wafers. A second semiconductor wafer and a first semiconductor wafer are attached by a bonding layer/interface and the second semiconductor wafer undergoes a thinning process. As a part of the thinning process, a first protective layer is applied to the edges of the second and first semiconductor wafers. A third semiconductor wafer is attached to the second semiconductor wafer by a bonding layer/interface and the third semiconductor wafer undergoes a thinning process. As a part of the thinning process, a second protective layer is applied to the edges of the third semiconductor wafer and over the first protective layer. The first, second and third semiconductor wafers form a wafer stack. The wafer stack is diced into a plurality of 3D chips while maintaining the first and second protective layers. | 12-12-2013 |
20140113433 | WAFER BONDING FOR 3D DEVICE PACKAGING FABRICATION - An apparatus and method bond a first wafer to a second wafer. The apparatus includes a first pressure application device configured to apply pressure at a central region of the first wafer in a direction toward the second wafer to initiate a bonding process between the first wafer and the second wafer. The apparatus also includes one or more second pressure application devices configured to apply pressure between the central region and an outer edge of the first wafer to complete the bonding process. The one or more second pressure application devices apply pressure on the first wafer after the first pressure application device has initiated the bonding process and while the first pressure application device continues to apply pressure at the central region. A controller controls the first pressure application device and the one or more second pressure application devices. | 04-24-2014 |
20140199628 | LITHOGRAPHIC MATERIAL STACK INCLUDING A METAL-COMPOUND HARD MASK - A lithographic material stack including a metal-compound hard mask layer is provided. The lithographic material stack includes a lower organic planarizing layer (OPL), a dielectric hard mask layer, and the metal-compound hard mask layer, an upper OPL, an optional anti-reflective coating (ARC) layer, and a photoresist layer. The metal-compound hard mask layer does not attenuate optical signals from lithographic alignment marks in underlying material layers, and can facilitate alignment between different levels in semiconductor manufacturing. | 07-17-2014 |
20140199832 | TITANIUM OXYNITRIDE HARD MASK FOR LITHOGRAPHIC PATTERNING - A vertical stack including a dielectric hard mask layer and a titanium nitride layer is formed over an interconnect-level dielectric material layer such as an organosilicate glass layer. The titanium nitride layer may be partially or fully converted into a titanium oxynitride layer, which is subsequently patterned with a first pattern. Alternately, the titanium nitride layer, with or without a titanium oxynitride layer thereupon, may be patterned with a line pattern, and physically exposed surface portions of the titanium nitride layer may be converted into titanium oxynitride. Titanium oxynitride provides etch resistance during transfer of a combined first and second pattern, but can be readily removed by a wet etch without causing surface damages to copper surfaces. A chamfer may be formed in the interconnect-level dielectric material layer by an anisotropic etch that employs any remnant portion of titanium nitride as an etch mask. | 07-17-2014 |
20140261960 | WAFER-TO-WAFER OXIDE FUSION BONDING - Oxide-oxide fusion bonding of wafers that includes performing a van der Waals force bonding process with a chuck having at least a flat central zone and an outer annular zone lower than the central zone, an edge portion of a mounted wafer is biased towards the outer annular zone. The van der Waals bonding wave is disrupted at the outer annular zone, causing an edge gap. A thermocompression bonding process is performed that includes heating the bonded wafers to a temperature sufficient to initiate condensation of silanol groups between the bonding surfaces, reducing the atmospheric pressure to cause degassing from between the wafers, applying a compression force to the wafers with flat chucks so as to substantially eliminate the edge gap, and performing a permanent anneal bonding process. | 09-18-2014 |
20140265165 | WAFER-TO-WAFER FUSION BONDING CHUCK - A chuck face of a wafer bonding chuck that includes a flat central zone and an outer annular zone contiguous to the central zone, the outer annular zone being lower than the flat central zone such that an annular edge portion of a wafer that is mounted to the chuck face has a convex profile with respect to the chuck face of the bonding chuck. The outer annular zone may move along an axis that is perpendicular to the central zone. The chuck face may include a plurality of contiguous zones, with at least one of the zones moveable with respect to another of the zones. | 09-18-2014 |
20140273425 | CYCLICAL PHYSICAL VAPOR DEPOSITION OF DIELECTRIC LAYERS - Embodiments include methods of forming dielectric layers. According to an exemplary embodiment, a dielectric layer may be formed by determining a desired thickness of the dielectric layer, forming a first dielectric sub-layer having a thickness less than the desired thickness by depositing a first metal layer above a substrate and oxidizing the first metal layer, and forming n (where n is greater than 1) additional dielectric sub-layers having a thickness less than the desired thickness above the first dielectric sub-layer by the same method of the first dielectric sub-layer so that a combined thickness of all dielectric sub-layers is approximately equal to the desired thickness. | 09-18-2014 |
20140353828 | SUBSTRATE BONDING WITH DIFFUSION BARRIER STRUCTURES - A metallic dopant element having a greater oxygen-affinity than copper is introduced into, and/or over, surface portions of copper-based metal pads and/or surfaces of a dielectric material layer embedding the copper-based metal pads in each of two substrates to be subsequently bonded. A dopant-metal silicate layer may be formed at the interface between the two substrates to contact portions of metal pads not in contact with a surface of another metal pad, thereby functioning as an oxygen barrier layer, and optionally as an adhesion material layer. A dopant metal rich portion may be formed in peripheral portions of the metal pads in contact with the dopant-metal silicate layer. A dopant-metal oxide portion may be formed in peripheral portions of the metal pads that are not in contact with a dopant-metal silicate layer. | 12-04-2014 |
20140353839 | MANGANESE OXIDE HARD MASK FOR ETCHING DIELECTRIC MATERIALS - A manganese oxide layer is deposited as a hard mask layer on substrate including at least a dielectric material layer. An optional silicon oxide layer may be formed over the manganese oxide layer. A patterned photoresist layer can be employed to etch the optional silicon oxide layer and the manganese oxide layer. An anisotropic etch process is employed to etch the dielectric material layer within the substrate. The dielectric material layer can include silicon oxide and/or silicon nitride, and the manganese oxide layer can be employed as an effective etch mask that minimizes hard mask erosion and widening of the etched trench. The manganese oxide layer may be employed as an etch mask for a substrate bonding process. | 12-04-2014 |
20140356983 | DISTORTING DONOR WAFER TO CORRESPONDING DISTORTION OF HOST WAFER - A method generally for improving wafer-to-wafer bonding alignment. Planar distortions of the bonding surface of a host wafer are determined. The bonding surface of a donor wafer is distorted such that the distortions of the donor wafer bonding surface correspond to the determined planar distortions of the host wafer bonding surface. Also, a method to separate bonded wafers. A bonded wafer pair is mounted between first and second bonding chucks having flat chuck faces, the first bonding chuck face including adjustable zones capable of movement relative to each other, at least a component of the relative movement is along an axis that is perpendicular to the flat first bonding chuck face. The adjustable zones of the first face are moved relative to each other in a coordinated manner such that a widening gap is formed between the bonding faces of the wafer pair. | 12-04-2014 |