Patent application number | Description | Published |
20080232529 | COMMUNICATION SYSTEM - To obtain a frame synchronization device and a frame synchronization method capable of preventing a malfunction when a frame is synchronized by using a frame synchronization pattern varying sequentially. A bit serial signal at every frame is transmitted sequentially in a shift register composed of flip-flop circuits. When a bit in each of the stages is detected to be coincided with a corresponding bit in a frame synchronization pattern by coincidence circuits, existence of a synchronized frame is determined. Each bit in the synchronization pattern is also inputted into an all-zero detection circuit. If an all-zero state is detected, a first AND circuit does not output a synchronization pattern detecting signal even with a case where coincidence is detected from the coincidence circuits. | 09-25-2008 |
20090207960 | FRAME PULSE SIGNAL LATCH CIRCUIT AND PHASE ADJUSTMENT METHOD - While a phase of an output clock signal is varied, an input frame pulse is latched based on the output clock signal. Then, by using an output frame pulse, which is a result of the latching, generation of a racing state, which is caused by the phase relation between the output clock signal and the output frame pulse, is detected. Next, a phase adjustment amount is determined so that the phase of the output clock signal of the moment when the racing state is generated is shifted by a period corresponding to half a cycle of the output clock signal. | 08-20-2009 |
20090212836 | FRAME PULSE SIGNAL LATCH CIRCUIT AND PHASE ADJUSTMENT METHOD - A frame pulse signal latch circuit has: a pulse-width expanding unit which outputs a frame pulse signal FPIN having a pulse width longer than a m-clock cycle; a phase adjustment unit which generates a phase-adjusted output clock CLKâ²; a flip-flop which latches the frame pulse signal FPIN; a racing detection unit which generates signals, which are shifted by one to m clocks with respect to a frame pulse signal FPOUT, and detects a racing state based on a result of an AND operation of the frame pulse signal FPOUT and the clock-shifted signals; and a control unit which sequentially selects and directs different phase adjustment amounts to the phase adjustment unit, determines an optimal phase adjustment amount based on a worst phase adjustment amount of the case in which the racing state is detected, and gives a direction about the optimal phase adjustment amount to the phase adjustment unit. | 08-27-2009 |
20110302464 | DIGITAL DATA TRANSMISSION SYSTEM USING TRANSMITTING UNIT AND RECEIVING UNIT AND TRANSMISSION METHOD - A digital data transmission system includes a transmission unit and a reception unit. The transmission unit includes: a transmission-side logic section configured to transmit digital data in parallel onto data lines; and a deskew data generating section configured to transmit deskew data onto a deskew signal line. The deskew data includes sample data and parity data for each of line components of the digital data. The reception unit includes: a skew adjusting section configured to perform deskew processing on the digital data recovered from the data transmitted on the data lines based on the deskew data recovered from the data transmitted on the deskew signal line; an error correcting section configured to perform error correction on the recovered digital data subjected to the deskew processing based on the parity data of the recovered deskew data; and a reception-side logic section configured to execute a predetermined process to the recovered digital data subjected to the error correction. | 12-08-2011 |
20120011417 | PLI N-BIT CORRECTION CIRCUIT, GFP LAYER 2 SYNCHRONIZATION CIRCUIT AND GFP FRAME TRANSFER DEVICE USING IT - A PLI n-bit correction circuit extracts a core header (PLI) from a GFP frame with a fixed payload length; compares it with a predetermined expectation value for each bit; calculates the number of inconsistent bits therebetween; and outputs the predetermined expectation value, instead of the core header, when the number of inconsistent bits is equal to or less than n (n is a natural number); or directly outputs the core header when the number of inconsistent bits is greater than n. A decision on establishment of GFP Layer 2 synchronization is made based on the output of the PLI n-bit correction circuit, wherein predetermined processing is executed on a payload of a GFP frame dropping its core header when GFP Layer 2 synchronization is established, whilst the payload is not subjected to predetermined processing and discarded in the event of GFP Layer 2 desynchronization. | 01-12-2012 |
20120027107 | COMMUNICATION DEVICE AND COMMUNICATION METHOD IN DATA TRANSMISSION SYSTEM - A communication device includes: a detector for detecting a predetermined number of consecutive identical codes from first data for transmission to generate a bit inversion instruction signal; a data inversion section for inversing at least one bit of the first data when the bit inversion instruction signal is generated; and a transmitter for transmitting the second data to another communication device. The predetermined number is not greater than a specified number of consecutive identical codes in the data transmission system. | 02-02-2012 |
20120117447 | Data transmission - If the number of bits at which 64-bit width data has changed at the same time has exceeded a threshold, the data is outputted, with the polarity of each bit inverted. Otherwise, the data is outputted. A 7-bit width error correcting code is given to the outputted data and the inversion instruction signal indicating whether the number of the changed bits has exceeded the threshold. Error code correction is performed for the data and the inversion instruction signal with the use of the transmitted error correcting code. If the inversion instruction signal for which the error code correction has been performed indicates that the number of the changed bits has exceeded the threshold, the data for which the error code correction has been performed is outputted, with the polarity of each bit inverted. Otherwise, the data for which the error code correction has been performed is outputted. | 05-10-2012 |
20130064252 | SIGNAL TRANSMISSION/RECEPTION CIRCUIT - The code word generation section generates a code word by adding an error checking and correcting code to an word. The conversion section divides the code words into bit strings each including information bits having the same number of bits as that of the word and code bits having the same number of bits as that of the error checking and correction code, and for each of the bit strings, outputs the information bits of the bit string to a first signal line group and outputs the code bits to a second signal line group. When dividing the code words into the bit strings, the code words are divided in such a manner as to satisfy a condition that a plurality of bits of the same code word are not output at the same time on a particular signal line group. | 03-14-2013 |
20130067296 | SIGNAL TRANSMISSION/RECEPTION CIRCUIT - A data buffer section stores input words, and outputs them to a first signal line group in order. An error checking and correcting code is generated that has the same number of bits as the words. Some bits are not to be output at the same time within the range of the first and second signal line groups or within the range of a partial signal line group included in the first and second signal line groups. A code transmission section outputs the error checking and correcting code to different signal lines of the second signal line group respectively, such that a plurality of bits in a code word are not output at the same time within the range of the first and second signal line groups or within the range of a partial signal line group included in the first and second signal line groups. | 03-14-2013 |