Patent application number | Description | Published |
20110080388 | DISPLAY PANEL AND ACTIVE DEVICE ARRAY SUBSTRATE THEREOF - A display panel including an active device array substrate, an opposite substrate and a display medium is provided. The active device array substrate includes a substrate, scan lines, data lines, pixel units, and data signal transmission lines. The scan lines and data lines define a plurality of pixel regions on the substrate. Each pixel unit is disposed within one of the pixel regions respectively, and each pixel unit includes a plurality of sub-pixel units. The sub-pixel units within the same pixel unit are electrically connected with the same data line, and each sub-pixel unit within the same pixel unit is electrically connected with one of the scan lines respectively. Each data signal transmission line is electrically connected with one of the data lines, and an extending direction of the data signal transmission line is substantially parallel with an extending direction of the scan lines. | 04-07-2011 |
20110233567 | PIXEL ARRAY - A pixel array is located on a substrate and includes a plurality of pixel sets. Each of the pixel sets includes a first scan line, a second scan line, a data line, a data signal transmission line, a first pixel unit, and a second pixel unit. The data line is not parallel to the first and the second scan lines. The data signal transmission line is disposed parallel to the first and the second scan lines and electrically connected to the data line. Distance between the first and the second scan lines is smaller than distance between the data signal transmission line and one of the first and the second scan lines. The first pixel unit is electrically connected to the first scan line and the data line. The second pixel unit is electrically connected to the second scan line and the data line. | 09-29-2011 |
20110273654 | ACTIVE DEVICE ARRAY SUBSTRATE - An active device array substrate includes a substrate, scan lines disposed on the substrate, data lines intersected with the scan lines, scan signal transmission lines, and pixel units. The scan signal transmission lines are intersected with the scan lines. Each scan signal transmission line connects one scan line through a node. The pixel unit electrically connects the corresponding data line and the corresponding scan line and includes an active device and a pixel electrode. The active device has a gate, a source, and a drain. The pixel electrode electrically connects the drain. In the pixel units not adjacent to the nodes, a gate-to-drain capacitance of each active device is Cgd | 11-10-2011 |
20110292331 | PIXEL STRUCTURE AND DISPLAY PANEL HAVING THE SAME - A pixel structure includes a first and a second scan lines, a data line, a first insulating layer covering the first and the second scan lines and a portion of the data line and having a recess, a second insulating layer covering the first insulating layer, a capacitor electrode line covering the data line and the recess, a third insulating layer on the capacitor electrode line, a first active device electrically connected to the second scan line and the data line, a second active device electrically connected to the first active device and the first scan line, and a first and a second pixel electrodes electrically connected to the first and the second active devices, respectively. The portion of the data line and the first and the second scan lines are in the same layer. The recess is located at two sides of the portion of the data line. | 12-01-2011 |
20120169677 | LIQUID CRYSTAL DISPLAY AND LIQUID CRYSTAL DISPLAY PANEL THEREOF - A liquid crystal display (LCD) and an LCD panel thereof are provided. The structure of the pixel array of the LCD panel is the structure of the one third source driving (OTSD), and by which skillfully layout the coupled relationship among each pixel, each signal line and each scan line, such that the LCD panel can be driven by a column inversion to achieve the purpose of single-dot inversion displaying, and thus not only reducing the power consumption of the whole LCD, but also promoting the display quality. | 07-05-2012 |
20120315733 | METHOD OF FABRICATING GATE ELCTRODE USING A TREATED HARD MASK - A hard mask layer with a limited thickness is formed over a gate electrode layer. A treatment is provided on the hard mask layer to transform the hard mask layer to be more resistant to wet etching solution. A patterning is provided on the treated hard mask layer and the gate electrode to from a gate structure. | 12-13-2012 |
20130009216 | Semiconductor Device With a Dislocation Structure and Method of Forming the Same - A semiconductor device with bi-layer dislocation and method of fabricating the semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility. The method includes providing a substrate having a gate stack. The method further includes performing a first pre-amorphous implantation process on the substrate and forming a first stress film over the substrate. The method also includes performing a first annealing process on the substrate and the first stress film. The method further includes performing a second pre-amorphous implantation process on the annealed substrate, forming a second stress film over the substrate and performing a second annealing process on the substrate and the second stress film. | 01-10-2013 |
20130146895 | PINCH-OFF CONTROL OF GATE EDGE DISLOCATION - The embodiments of processes and structures described provide mechanisms for improving the mobility of carriers. A dislocation is formed in a source or drain region between gate structures or between a gate structure and an isolation structure by first amortizing the source or drain region and then recrystallizing the region by using an annealing process with a low pre-heat temperature. A doped epitaxial material may be formed over the recrystallized region. The dislocation and the strain created by the doped epitaxial material in the source or drain region help increase carrier mobility. | 06-13-2013 |
20130146949 | MECHANISMS FOR FORMING STRESSOR REGIONS IN A SEMICONDUCTOR DEVICE - The embodiments of processes and structures described above provide mechanisms for improving mobility of carriers. The dislocations in the source and drain regions and the strain created by the doped epitaxial materials next to the channel region of a transistor both contribute to the strain in the channel region. As a result, the device performance is improved. | 06-13-2013 |
20130157431 | STRUCTURE AND METHOD FOR THERMAL TREATMENT WITH EPITAXIAL SICP THERMAL STABILITY IMPROVEMENT - The present disclosure provides a method for making an integrated circuit in one embodiment. The method includes providing a semiconductor substrate having an active region and a first gate stack disposed on the semiconductor substrate in the active region; forming in-situ phosphorous-doped silicon carbide (SiCP) features on the semiconductor substrate and disposed on sides of the first gate stack; replacing the first gate stack with a second gate stack having a high k dielectric material layer; and thereafter performing a millisecond annealing (MSA) process with a thermal profile having a first thermal wavelet and a second thermal wavelet. | 06-20-2013 |
20130178029 | METHOD OF FORMING A SEMICONDUCTOR DEVICE - A semiconductor device having dislocations and a method of fabricating the semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility. The method includes providing a substrate having an isolation feature therein and two gate stacks overlying the substrate, wherein one of the gate stacks is atop the isolation feature. The method further includes performing a pre-amorphous implantation process on the substrate. The method further includes forming spacers adjoining sidewalls of the gate stacks, wherein at least one of the spacers extends beyond an edge the isolation feature. The method further includes forming a stress film over the substrate. The method also includes performing an annealing process on the substrate and the stress film. | 07-11-2013 |
20140154876 | MECHANISMS FOR FORMING STRESSOR REGIONS IN A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes performing a pre-amorphous implantation (PAI) process to form an amorphized region on a substrate. The method also includes forming a stress film over the substrate, and performing an annealing process to recrystallize the amorphized region after the stress film is formed. The method further includes forming a recess region on the substrate. The recess region overlies the recrystallized region. The method additionally includes forming an epitaxial stress-inducing material in the recess region. | 06-05-2014 |
20140220757 | PINCH-OFF CONTROL OF GATE EDGE DISLOCATION - A method of manufacturing a semiconductor device includes providing a substrate having a gate stack, and performing a pre-amorphous implantation (PAI) process to form an amorphized region on the substrate. The method also includes performing an annealing process to recrystallize the amorphized region after the stress film is formed. The annealing process includes a preheat at a temperature in a range from about 400° C. to about 550° C. and an annealing temperature equal to or greater than about 900° C., and the annealing process recrystallizes the amorphized region. | 08-07-2014 |