Tsai, Hsin-Chu City
Cheng-Lung Tsai, Hsin-Chu City TW
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20110161907 | Practical Approach to Layout Migration - The present disclosure provides an integrated circuit design method in many different embodiments. An exemplary IC design method comprises providing an IC design layout of a circuit in a first technology node; migrating the IC design layout of the circuit to a second technology node; applying an electrical patterning (ePatterning) modification to the migrated IC design layout according to an electrical parameter of the circuit; and thereafter fabricating a mask according to the migrated IC design layout of the circuit in the second technology node. | 06-30-2011 |
20110204470 | METHOD, SYSTEM, AND APPARATUS FOR ADJUSTING LOCAL AND GLOBAL PATTERN DENSITY OF AN INTEGRATED CIRCUIT DESIGN - An integrated circuit (IC) design method providing a circuit design layout having a plurality of functional blocks disposed a distance away from each other; identifying a local pattern density to an approximate dummy region, on the circuit design layout, within a predefined distance to one of the functional blocks; performing a local dummy insertion to the approximate dummy region according to the local pattern density; repeating the identifying and performing to at least some other of the functional blocks; and implementing a global dummy insertion to a non-local dummy region according to a global pattern density. | 08-25-2011 |
20110214101 | METHOD OF THERMAL DENSITY OPTIMIZATION FOR DEVICE AND PROCESS ENHANCEMENT - The present disclosure provides an integrated circuit method. The method includes providing an integrated circuit (IC) design layout; simulating thermal effect to the IC design layout; simulating electrical performance to the IC design layout based on the simulating thermal effect; and performing thermal dummy insertion to the IC design layout based on the simulating electrical performance. | 09-01-2011 |
20140007024 | Pattern Recognition For Integrated Circuit Design | 01-02-2014 |
20150161321 | POLYGON-BASED OPTICAL PROXIMITY CORRECTION - Methods and systems for design of integrated circuits including performing OPC are discussed. In one embodiment, design data having a geometric feature is provided. A base feature is formed from the geometric feature, which has a substantially linear edge. A pseudo dissection point is determined on the base feature. Add or trim a polygon from the base feature to form a modified feature. An OPC process is performed on the modified feature to generate an output design. The output design is used to fabricate a semiconductor device on a semiconductor substrate. | 06-11-2015 |
Chia-Fen Tsai, Hsin-Chu City TW
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20110156078 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor light-emitting device includes a light-impervious substrate, a bonding structure, a semiconductor light-emitting stack, and a fluorescent material structure overlaying the semiconductor light-emitting stack. The semiconductor light-emitting stack is separated from a growth substrate and bonded to the light-impervious substrate via the bonding structure. A method for producing the semiconductor light-emitting device includes separating a semiconductor light-emitting stack from a growth substrate, bonding the semiconductor light-emitting stack to a light-impervious substrate, and forming a fluorescent material structure over the semiconductor light-emitting stack. | 06-30-2011 |
20150044794 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor light-emitting device includes a light-impervious substrate, a bonding structure, a semiconductor light-emitting stack, and a fluorescent material structure overlaying the semiconductor light-emitting stack. The semiconductor light-emitting stack is separated from a growth substrate and bonded to the light-impervious substrate via the bonding structure. A method for producing the semiconductor light-emitting device includes separating a semiconductor light-emitting stack from a growth substrate, bonding the semiconductor light-emitting stack to a light-impervious substrate, and forming a fluorescent material structure over the semiconductor light-emitting stack. | 02-12-2015 |
Chia-Hsun Tsai, Hsin-Chu City TW
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20080278942 | DIRECT-TYPE BACKLIGHT MODULE AND LAMP HOLDER THEREOF - A direct-type backlight module and a lamp holder thereof are disclosed. The lamp holder includes a plurality of lamp seats, and a plurality of connecting arms each connected with at least one adjacent lamp seat. Each lamp seat has a retaining portion for retaining a corresponding lamp therein. Each connecting arm has a bendable portion that can be bent along a horizontal direction so as to adjust a distance between adjacent lamp seats. Therefore, the lamp holder of the present invention has a capability to retain several lamp groups spaced at different intervals for different LCD types or with lamp assembly tolerances, and thereby achieves a higher convenience in the LCD assembly. | 11-13-2008 |
Chia-Ku Tsai, Hsin-Chu City TW
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20150109705 | METHOD AND ASSOCIATED APPARATUS FOR PERFORMING ELECTROSTATIC DISCHARGE PROTECTION - A method for performing electrostatic discharge (ESD) protection and an associated apparatus are provided, where the method is applied to an electronic device, and the method includes: utilizing a trigger source formed with a plurality of Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) to trigger a discharge operation, where the gate and the drain of any MOSFET within the plurality of MOSFETs are electrically connected to each other, causing the MOSFET to be utilized as a two-terminal component, and the MOSFETs that are respectively utilized as two-terminal components are connected in series; and utilizing an ESD apparatus to perform the discharge operation in response to the trigger of the trigger source, in order to perform ESD protection on the apparatus. | 04-23-2015 |
Chia-Shiung Tsai, Hsin-Chu City TW
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20150060964 | MECHANISMS FOR FORMING IMAGE SENSOR DEVICE - Embodiments of mechanisms for forming an image sensor device are provided. The image sensor device includes a semiconductor substrate and one photodetector formed in the semiconductor substrate. The image sensor device also includes one gate stack formed over the semiconductor substrate. The gate stack includes multiple polysilicon layers. | 03-05-2015 |
20150280004 | EMBEDDED NONVOLATILE MEMORY - A nonvolatile memory embedded in an advanced logic circuit and a method forming the same are provided. In the nonvolatile memory, the word lines and erase gates have top surfaces lower than the top surfaces of the control gate. In addition, the word lines and the erase gates are surrounded by dielectric material before a self-aligned silicidation process is performed. Therefore, no metal silicide can be formed on the word lines and the erase gate to produce problems of short circuit and current leakage in a later chemical mechanical polishing process. | 10-01-2015 |
Chun-Hui Tsai, Hsin-Chu City TW
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20090273294 | FLAT DISCHARGE LAMP AND PRODUCTION METHOD THEREOF - The present invention provides a flat discharge lamp and the production method thereof. The flat discharge lamp comprises an upper substrate, a lower substrate and a discharge chamber disposed between the upper substrate and the lower substrate, wherein the discharge chamber is filled with an inert gas, and a plurality of first electrodes and second electrodes are arranged with one another disposed on the discharge chamber. Besides, each of the first electrodes and second electrodes is connected with one end and another end of an alternating power supply, respectively. The invention is characterized in that the discharge chamber is provided with fluorescent film coated on its interior surface and a plurality of third electrodes each disposed between the first electrode and the second electrode. Besides, all the third electrodes are connected to a common plane, or each of which is connected to the common plane, respectively. The third electrode is controllable to change the discharge energy and path when dielectrically impeded discharge is carried out between the first electrode and the second electrode. | 11-05-2009 |
20100020113 | ELECTRONIC DISPLAY MODULE AND DISPLAYING METHOD THEREOF - The present invention provides an electronic display module and displaying method thereof. The electronic display module includes a light source, a filter and a light valve. The electronic display module further has a display panel with a plurality of display regions for displaying an image. The electronic display module is provided to adjust the light intensity by space and time varying luminance of the light source, so as to enable the electronic display module to present the image in dynamic display according to the space and time varying approach. | 01-28-2010 |
Chun Lin Tsai, Hsin-Chu City TW
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20130313617 | Embedded JFETs for High Voltage Applications - A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET. | 11-28-2013 |
20140054708 | Stacked and Tunable Power Fuse - The present disclosure provides a semiconductor device that includes a transistor including a substrate, a source, a drain, and a gate, and a fuse stacked over the transistor. The fuse includes an anode contact coupled to the drain of the transistor, a cathode contact, and a resistor coupled to the cathode contact and the anode contact via a first Schottky diode and a second Schottky diode, respectively. A method of fabricating such semiconductor devices is also provided. | 02-27-2014 |
Fei-Gwo Tsai, Hsin-Chu City TW
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20080248404 | Method for Controlling Phase Angle of a Mask by Post-Treatment - A method for controlling phase angle of a mask is provided. A mask comprising a substrate and an absorber is formed. A nitrogen-containing plasma treatment is performed on the mask to reduce the phase angle. Alternatively, a nitrogen-containing plasma treatment is performed on the mask, followed by a vacuum ultraviolet treatment to form a passivated layer on the mask. | 10-09-2008 |
Fu-Yi Tsai, Hsin-Chu City TW
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20150109705 | METHOD AND ASSOCIATED APPARATUS FOR PERFORMING ELECTROSTATIC DISCHARGE PROTECTION - A method for performing electrostatic discharge (ESD) protection and an associated apparatus are provided, where the method is applied to an electronic device, and the method includes: utilizing a trigger source formed with a plurality of Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) to trigger a discharge operation, where the gate and the drain of any MOSFET within the plurality of MOSFETs are electrically connected to each other, causing the MOSFET to be utilized as a two-terminal component, and the MOSFETs that are respectively utilized as two-terminal components are connected in series; and utilizing an ESD apparatus to perform the discharge operation in response to the trigger of the trigger source, in order to perform ESD protection on the apparatus. | 04-23-2015 |
Hao-Yi Tsai, Hsin-Chu City TW
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20080217735 | Metal e-Fuse structure design - An integrated circuit structure is provided. The integrated circuit structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; a metal fuse in the dielectric layer; a dummy pattern adjacent the metal fuse; and a metal line in the dielectric layer, wherein a thickness of the metal fuse is substantially less than a thickness of the metal line. | 09-11-2008 |
20080246031 | PCM pad design for peeling prevention - A semiconductor structure is provided. The semiconductor structure includes a semiconductor chip and a scribe line adjoining the semiconductor chip. A conductive feature is formed in the scribe line and exposed on the surface of the scribe lines, wherein the conductive feature has an edge facing the semiconductor chip. A kerf path is in the scribe line. A first cut is formed in the conductive feature, wherein the first cut extends from the first edge to the kerf path. | 10-09-2008 |
20110079922 | INTEGRATED CIRCUIT WITH PROTECTIVE STRUCTURE, AND METHOD OF FABRICATING THE INTEGRATED CIRCUIT - A structure includes a semiconductor substrate having semiconductor devices formed on or in the substrate. An interconnecting metallization structure is formed over and connected to the devices. The interconnecting metallization structure including at least one dielectric layer. A passivation layer is deposited over the interconnecting metallization structure and the dielectric layer. At least one metal contact pad and at least one dummy metal structure are provided in the passivation layer. The contact pad is conductively coupled to at least one of the devices. The dummy metal structure is spaced apart from the contact pad and unconnected to the contact pad and the devices. | 04-07-2011 |
Kuo-Shih Tsai, Hsin-Chu City TW
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20090177723 | METHOD AND APPARATUS FOR APPROXIMATING AN UPPER-BOUND LIMIT FOR AN ABSOLUTE VALUE OF A COMPLEX NUMBER OR NORM OF A TWO-ELEMENT VECTOR - A method for approximating an upper bound limit for the absolute value of a complex number or the norm of a two-element vector is disclosed. An upper bound approximation algorithm is used to minimize software implementation efforts and make the hardware implementation less expensive. The hardware implementation of the upper bound approximation algorithm only requires a multiplier element and an adder element. Therefore, this algorithm can be implemented anywhere in a digital signal processing apparatus without increasing cost significantly. Moreover, the hardware employing the present invention can be implemented in a pipeline architecture configuration to achieve a real time function in digital audio or digital video applications. | 07-09-2009 |
Meng-Chieh Tsai, Hsin-Chu City TW
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20110148860 | STEREOSCOPIC DISPLAY - A stereoscopic display is proposed. A first display zone and a second display zone are displayed based on light for a first light source group, in response to a first data voltage signal fed to the first display zone and the second display zone, and to a second data voltage signal fed to a third display zone. The second display zone and the third display zone are displayed based on light for a second light source group, in response to the second data voltage signal fed to the first display zone, and to the first data voltage signal fed to the second display zone and the third display zone. The first display zone and the second display zone are displayed based on light from the first light source group, in response to the second data voltage signal fed to the first display zone and the second display zone, and to the first data voltage signal fed to the third display zone. The second display zone and the third display zone are displayed based on light from the second light source group, in response to the first data voltage signal fed to the first display zone, and to the second data voltage signal fed to the second display zone and the third display zone. | 06-23-2011 |
Ming-Chieh Tsai, Hsin-Chu City TW
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20090315841 | Touchpad Module which is Capable of Interpreting Multi-Object Gestures and Operating Method thereof - A touchpad module, capable of interpreting multi-object gestures and an operating method, includes a detecting element for detecting an object amount and gesture made from a conductive object placed on the touchpad surface and a processing element for interpreting and driving a corresponding simulation such as a mouse, a keyboard or a hot-key simulation and thus controlling a change of document, icon, picture or frame displayed on a display. Accordingly, the touchpad and the operating method thereof detect and interpret multi-object gestures so that it may simulate the input operation with the input devices such as a mouse and a keyboard and the selection of hot-key functions provided by various application programs. | 12-24-2009 |
Ming-Chin Tsai, Hsin-Chu City TW
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20080301073 | METHOD FOR WAFER ANALYSIS WITH ARTIFICIAL NEURAL NETWORK AND SYSTEM THEREOF - A method for wafer analysis with artificial neural network and the system thereof are disclosed. The method of the system of the present invention has several steps, including: first of all, providing a test unit for wafer test and generating a plurality of test data; next, transmitting the test data to a processing unit for transferring to output data; then, comparing the output data with predictive value and modifying bias and making the output data close to the predictive value, and repeating the steps mentioned above to train this system; finally, analyzing wafers by the trained system. Using this system to analyze wafers not only saves time, but also reduces manpower and the risk resulting from artificial analysis. | 12-04-2008 |
20100030513 | Method for Disposing Power/Ground Plane of PCB - A method for disposing power planes and ground planes of a printed circuit board (PCB), said method comprising the steps of: providing a PCB on which is disposed with a geometric layout and a via hole; providing a line on said PCB for intersecting said geometric layout to form a plurality of points of intersection; defining line segments by segmenting said line at each of said points of intersection to form a plurality of line segments; deleting some of said line segments having one end not being point of intersection for said geometric layout to form a plurality of segmented regions; searching a closed region by repeatedly searching region from any one of the points in said plurality of segmented regions; determining whether a closed region is a smallest closed region; determining whether a via hole is located within said smallest closed region. | 02-04-2010 |
20130149871 | CHEMICAL VAPOR DEPOSITION FILM PROFILE UNIFORMITY CONTROL - The present disclosure provides for methods and systems for controlling profile uniformity of a chemical vapor deposition (CVD) film. A method includes depositing a first layer on a substrate by CVD with a first shower head, the first layer having a first profile, and depositing a second layer over the first layer by CVD with a second shower head, the second layer having a second profile. The combined first layer and second layer have a third profile, and the first profile, the second profile, and the third profile are different from one another. | 06-13-2013 |
Nien-Tsung Tsai, Hsin-Chu City TW
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20140117510 | Semiconductor Bonding Structure and Process - A system and method for bonding semiconductor devices is provided. An embodiment comprises halting the flow of a eutectic bonding material by providing additional material of one of the reactants in a grid pattern, such that, as the eutectic material flows into the additional material, the additional material will change the composition of the flowing eutectic material and solidify the material, thereby stopping the flow. Other embodiments provide for additional layouts to put the additional material into the path of the flowing eutectic material. | 05-01-2014 |
Shau-Yu Tsai, Hsin-Chu City TW
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20110072653 | Light Emitting Device and Manufacture Method Thereof - A manufacture method of a light emitting device is provided. Firstly, at least one circuit board is provided. A plurality of light emitting packages, a first undetermined power input end and a second undetermined power input end are disposed at the circuit board. The light emitting packages are electrically connected to the first undetermined power input end and the second undetermined power input end. Each of the first undetermined power input end and the second undetermined power input end has at least two first pads. The first pads of each of the first undetermined power input end and the second undetermined power input end are electrically isolated from each other. Next, the first undetermined power input end is selected to be a power input region for inputting an external power signal. Then, the first pads of the second undetermined power input end are electrically connected to each other. | 03-31-2011 |
Tsung-Che Tsai, Hsin-Chu City TW
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20130341676 | Methods and Apparatus for Increased Holding Voltage in Silicon Controlled Rectifiers for ESD Protection - Methods and apparatus for increased holding voltage SCRs. A semiconductor device includes a semiconductor substrate of a first conductivity type; a first well of the first conductivity type; a second well of a second conductivity type adjacent to the first well, an intersection of the first well and the second well forming a p-n junction; a first diffused region of the first conductivity type formed at the first well and coupled to a ground terminal; a first diffused region of the second conductivity type formed at the first well; a second diffused region of the first conductivity type formed at the second well and coupled to a pad terminal; a second diffused region of the second conductivity type formed in the second well; and a Schottky junction formed adjacent to the first diffused region of the second conductivity type coupled to a ground terminal. Methods for forming devices are disclosed. | 12-26-2013 |
Wei-Chun Tsai, Hsin-Chu City TW
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20150287652 | Calculating Carrier Concentrations in Semiconductor Fins Using Probed Resistance - A method includes probing at least one semiconductor fin using a four-point probe head, with four probe pins of the four-point probe head contacting the at least one semiconductor fin. A resistance of the at least one semiconductor fin is calculated. A carrier concentration of the semiconductor fin is calculated from the resistance. | 10-08-2015 |
Wen-Sen Tsai, Hsin-Chu City TW
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20100162088 | XOR CIRCUIT, RAID DEVICE CAPABLE OF RECOVERING A PLURALITY OF FAILURES AND METHOD THEREOF - An XOR circuit, a RAID device which can recover several failures and method thereof are provided. A Galois field data recovery circuit having two or more sets of Galois Field engine circuits which are used in the XOR circuit, is one which can generate high efficient parity engine and high efficient flow data route and which at the same time correct the three or more failures during operation of the RAID device. | 06-24-2010 |
Yeou-Jyh Tsai, Hsin-Chu City TW
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20090135061 | METHOD AND DEVICE FOR PREDICTING GNSS SATELLITE TRAJECTORY EXTENSION DATA USED IN MOBILE APPARATUS - A method and device for predicting satellite trajectory extension data used in a mobile apparatus. The device in accordance with the present invention comprises an I/O interface and a microprocessor. The input/output (I/O) interface is used for obtaining at least one satellite navigation message for a satellite. The microprocessor is used for determining a propagating condition according to the satellite navigation message, estimating a plurality of parameters of a satellite trajectory prediction model according to the propagating condition, and propagating a set of satellite trajectory extension data by using the satellite trajectory prediction model. | 05-28-2009 |
20100289697 | METHOD AND DEVICE FOR PREDICTING GNSS SATELLITE TRAJECTORY EXTENSION DATA IN MOBILE APPARATUS - A method and device for predicting satellite trajectory extension data in a mobile apparatus. The device in accordance with the present invention comprises an I/O interface and a microprocessor. The input/output (I/O) interface is used for obtaining at least one satellite navigation message for at least one satellite. The microprocessor is used for determining a propagating condition according to the satellite navigation message, estimating at least one parameter of a satellite trajectory prediction model according to the propagating condition, and propagating at least one set of satellite trajectory extension data by using the satellite trajectory prediction model. | 11-18-2010 |
20110279316 | METHOD AND DEVICE FOR PREDICTING GNSS SATELLITE TRAJECTORY EXTENSION DATA IN MOBILE APPARATUS - A method and device for predicting satellite trajectory extension data in a mobile apparatus. The device in accordance with the present invention comprises an I/O interface and a microprocessor. The input/output (I/O) interface is used for obtaining at least one satellite navigation message for at least one satellite. The microprocessor is used for determining a satellite trajectory prediction model according to the satellite navigation message, and propagating at least one set of satellite trajectory extension data by using the satellite trajectory prediction model. | 11-17-2011 |
Yow-Fu Tsai, Hsin-Chu City TW
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20080267991 | IMMUNO-MODULATING ANTITUMOR ACTIVITIES OF GANODERMA LUCIDUM (REISHI) POLYSACCHARIDES - The present invention provides methods of modulating an immune response in an organism by administering medicinally active extracts and fractions, and a method for preparing the same by extracting and fractioning constituents from the tissue of components of | 10-30-2008 |
Yung-Sheng Tsai, Hsin-Chu City TW
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20080278942 | DIRECT-TYPE BACKLIGHT MODULE AND LAMP HOLDER THEREOF - A direct-type backlight module and a lamp holder thereof are disclosed. The lamp holder includes a plurality of lamp seats, and a plurality of connecting arms each connected with at least one adjacent lamp seat. Each lamp seat has a retaining portion for retaining a corresponding lamp therein. Each connecting arm has a bendable portion that can be bent along a horizontal direction so as to adjust a distance between adjacent lamp seats. Therefore, the lamp holder of the present invention has a capability to retain several lamp groups spaced at different intervals for different LCD types or with lamp assembly tolerances, and thereby achieves a higher convenience in the LCD assembly. | 11-13-2008 |