Tremaine, US
Brian Tremaine, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20110298695 | OPTICAL COMPONENT CALIBRATION SYSTEM FOR LASER-BASED DISPLAY DEVICE - A laser-based display device includes a plurality of ultraviolet lasers configured to excite a phosphor-containing display screen in order to produce visible light. The laser-based display device also includes a reference laser used for calibration operations. A control system within the laser-based display device causes the reference laser beam to scan across one or more calibration features, and adjusts optical components of the laser-based display device, including activation timing of the ultraviolet lasers, based on feedback patterns generated by the calibration features, to compensate for drift effects. The calibration features may be disposed off-screen or on-screen. | 12-08-2011 |
Dustin A. Tremaine, Kingsport, TN US
Patent application number | Description | Published |
---|---|---|
20130192779 | PROCESSES TO PRODUCE SHORT CUT MICROFIBERS - A process for producing a microfiber product stream, the process comprising: | 08-01-2013 |
20130192780 | PROCESSES TO PRODUCE SHORT CUT MICROFIBERS - A process for producing a microfiber product stream, the process comprising: | 08-01-2013 |
20130193085 | PROCESSES TO PRODUCE SHORT CUT MICROFIBERS - A process for producing a microfiber product stream is provided comprising: | 08-01-2013 |
20130193086 | PROCESSES TO PRODUCE SHORT CUT MICROFIBERS - A process for producing a microfiber product stream is provided comprising: | 08-01-2013 |
20130277320 | PROCESSES TO PRODUCE SHORT CUT MICROFIBERS - A process for separating a first mother liquor stream is provided. The process comprises: separating a first mother liquor stream in a second solid liquid separation zone to produce a secondary wet cake stream and a second mother liquor stream; wherein the first mother liquor stream comprises water non-dispersible microfiber, water, and water dispersible sulfopolyester; wherein the second mother liquor stream comprises water and water dispersible sulfopolyester; and wherein the secondary wet cake stream comprises water non-dispersible polymer microfiber. | 10-24-2013 |
John M. Tremaine, New Canaan, CT US
Patent application number | Description | Published |
---|---|---|
20090273425 | POWER SUPPLY CENTER - The present invention is related to power supply centers. The power supply centers of the present invention may be self-contained modular units. The power supply centers may have between one or more primary taps, a switch or dimmed tap to compensate for losses when dimming. The power supply centers may also have one or more secondary taps to provide secondary voltages of 11-30V depending upon the secondary voltage of the power supply center. Loads may be connected up the one or more secondary taps up to the full watt rating of the power supply center. In accordance with the power supply centers of the present invention, it is possible that loads at varying distances from the power supply center can be tapped on different taps to recover voltage drop and produce between 85% and 100% light output if the lighting system has been wired properly. | 11-05-2009 |
20090288877 | WIRE FITTING - The present invention is directed to a wire fitting that may be used to pass a wire, cable or other conductor through a surface in order to produce a substantially secure and water tight connection between the wire fitting, the wire and the surface. The wire fitting may include a cap unit that is configured to be removably affixed to a base unit. The cap unit and the base unit may include corresponding threads to allow the cap unit to be screwed onto the base unit. A compressible plug may be placed between the cap unit and base unit in an opening at an end of the base unit. A washer with a set of ridges may also be placed between the cap unit and the base unit on the compressible plug to facilitate compression of the compressible plug and secure the cap unit into place. | 11-26-2009 |
Michael C. Tremaine, San Diego, CA US
Patent application number | Description | Published |
---|---|---|
20090323557 | Method and Apparatus for Intertechnology IPv6 Address Configuration - Methods and apparatus for resolving incompatible network configurations are described herein. A mobile device having peripheral devices connected thereto receives a request from a peripheral device, determines whether the address configuration protocol associated with the peripheral device is compatible with the network to which the mobile device is connected, and if not compatible, the mobile device translates the address configuration protocol of the peripheral device to one compatible with the network. | 12-31-2009 |
20100023617 | Method and Apparatus for Ensuring IPv6 Uniqueness in a Mobile Subnetted Environment - A method and apparatus for ensuring network address uniqueness is described herein. An address manager determines whether any link-local addresses associated with peripheral devices connected to a mobile device would conflict with a network assigned global address. The address manager negotiates with the network to avoid conflicts. | 01-28-2010 |
Michael Colin Tremaine, San Diego, CA US
Patent application number | Description | Published |
---|---|---|
20150278684 | TIME SYNCHRONIZATION OF SPIKING NEURON MODELS ON MULTIPLE NODES - Certain aspects of the present disclosure support techniques for time synchronization of spiking neuron models that utilize multiple nodes. According to certain aspects, a neural model (e.g., of an artificial nervous system) may be implemented using a plurality of processing nodes, each processing node implementing a neuron model and communicating via the exchange of spike packets carrying information regarding spike information for artificial neurons. A mechanism may be provided for maintaining relative spike-timing between the processing nodes. In some cases, a mechanism may also be provided to alleviate deadlock conditions between the multiple nodes. | 10-01-2015 |
R. Brett Tremaine, Stormville, NY US
Patent application number | Description | Published |
---|---|---|
20090320006 | LEARNING AND CACHE MANAGEMENT IN SOFTWARE DEFINED CONTEXTS - A exemplary system and method are provided for learning and cache management in software defined contexts. Exemplary embodiments of the present invention described herein address the problem of the data access wall resulting from processor stalls due to the increasing discrepancies between processor speed and the latency of access to data that is not stored in the immediate vicinity of the processor requesting the data. | 12-24-2009 |
Robert Brett Tremaine, Stormville, NY US
Patent application number | Description | Published |
---|---|---|
20080263284 | Methods and Arrangements to Manage On-Chip Memory to Reduce Memory Latency - Methods, systems, and media for reducing memory latency seen by processors by providing a measure of control over on-chip memory (OCM) management to software applications, implicitly and/or explicitly, via an operating system are contemplated. Many embodiments allow part of the OCM to be managed by software applications via an application program interface (API), and part managed by hardware. Thus, the software applications can provide guidance regarding address ranges to maintain close to the processor to reduce unnecessary latencies typically encountered when dependent upon cache controller policies. Several embodiments utilize a memory internal to the processor or on a processor node so the memory block used for this technique is referred to as OCM. | 10-23-2008 |
20120198459 | ASSIST THREAD FOR INJECTING CACHE MEMORY IN A MICROPROCESSOR - A data processing system includes a microprocessor having access to multiple levels of cache memories. The microprocessor executes a main thread compiled from a source code object. The system includes a processor for executing an assist thread also derived from the source code object. The assist thread includes memory reference instructions of the main thread and only those arithmetic instructions required to resolve the memory reference instructions. A scheduler configured to schedule the assist thread in conjunction with the corresponding execution thread is configured to execute the assist thread ahead of the execution thread by a determinable threshold such as the number of main processor cycles or the number of code instructions. The assist thread may execute in the main processor or in a dedicated assist processor that makes direct memory accesses to one of the lower level cache memory elements. | 08-02-2012 |
Robert Brett Tremaine, Strormville, NY US
Patent application number | Description | Published |
---|---|---|
20100241900 | SYSTEM TO DETERMINE FAULT TOLERANCE IN AN INTEGRATED CIRCUIT AND ASSOCIATED METHODS - A system to determine fault tolerance in an integrated circuit may include a programmable logic device carried by the integrated circuit. The system may also include a configurable memory carried by the programmable logic device to control the function and/or connection of a portion of the programmable logic device. The system may further include user logic carried by said programmable logic device and in communication with a user and/or the configurable memory. The user logic may identify corrupted data in the configurable memory based upon changing user requirements. | 09-23-2010 |
Robert Brett Tremaine, Poughkeepsie, NY US
Patent application number | Description | Published |
---|---|---|
20110055777 | Verification of Soft Error Resilience - An efficient method for selecting a minimal and statistically relevant set of SER sensitive logic devices critical to the SER robustness for a design, through identification by device type, identification nomenclature, connectivity and context. The minimal set of devices comprise the set of fault injection test points using a conventional fault injection test verification environment to establish an SER induced failure rate a logic design. The selection method affords a design independent means to evaluate any design regardless of the origin, source language or documentation by working at the common logic device level “gate-level” netlist format for the design data. The selected set of devices is distilled from the design data by successively filtering the design through a series of heuristic rule-based device identifier computer programs that group and annotate the devices into specific database records. These records are then used to organize the fault injection device test set by test behavior and relevance. | 03-03-2011 |