Patent application number | Description | Published |
20090012729 | LIGHT RECEIVING APPARATUS, TESTING APPARATUS, LIGHT RECEIVING METHOD, TESTING METHOD, TEST MODULE AND SEMICONDUCTOR CHIP - An optical receiving apparatus that receives an optical signal and outputs a data value of digital data transmitted by the optical signal is provided, including a light receiving element that receives the optical signal and outputs a photocurrent according to a strength of the optical signal, a present cycle integrator that integrates the photocurrent corresponding to a present cycle of the digital data over a prescribed period within the cycle, a previous cycle integrator that integrates the photocurrent corresponding to a cycle prior to the present cycle over a period that is substantially equal to the prescribed period in the cycle, and a data value identifying circuit that outputs a data value of the present cycle of the digital data based on a difference between a charge amount obtained through integration by the present cycle integrator and a charge amount obtained through integration by the previous cycle integrator. | 01-08-2009 |
20090048796 | TEST APPARATUS - A test apparatus for testing a device under test includes a multi-strobe generating section that generates a plurality of strobe signals with different phases in each of cycles of an output signal output from the device under test, a plurality of timing comparing sections that obtain a value of the output signal respectively at timings of the plurality of strobe signals, a transition detecting section that generates transition data identifying one of the plurality of strobe signals which is positioned at a transition of the output signal, based on the values of the output signal which are respectively obtained at the timings of the plurality of strobe signals, a transition memory that sequentially stores thereon the transition data input thereto, a selecting section that selects, in association with each of the cycles of the output signal, whether to input the transition data output from the transition detecting section into the transition memory, and a calculating section that calculates jitter of the output signal based on the transition data stored on the transition memory. | 02-19-2009 |
20090058381 | POWER SUPPLY STABILIZING CIRCUIT, AN ELECTRONIC DEVICE AND A TEST APPARATUS - There is provided a power supply stabilizing circuit provided in a chip of an electronic device. The power supply stabilizing circuit stabilizes a power supply voltage supplied to an operational circuit of the electronic device, and includes a current bypass section that supplies a bypass current from an auxiliary power supply interconnection to a main power supply interconnection, where the main power supply interconnection supplies the power supply voltage to the operational circuit, and the auxiliary power supply interconnection is different from the main power supply interconnection, and a current control section that varies an amount of the bypass current supplied by the current bypass section to the main power supply interconnection in accordance with a predetermined current variation pattern, under an external control, during an operation of the operational circuit. | 03-05-2009 |
20090058456 | MANUFACTURING SYSTEM, MANUFACTURING METHOD, MANAGING APPARATUS, MANAGING METHOD AND COMPUTER READABLE MEDIUM - There is provided a manufacturing system for manufacturing an electronic device through a plurality of manufacturing stages. The manufacturing system includes a plurality of manufacturing apparatuses performing processes corresponding to the plurality of manufacturing stages. The manufacturing system includes a manufacturing line that manufactures the electronic device, a manufacturing control section that causes the manufacturing line to manufacture a wafer having therein a test circuit including a plurality of transistors under measurement, a measuring section that measures an electrical characteristic of each of the plurality of transistors under measurement in the test circuit, an identifying section that identifies, among the plurality of manufacturing stages, a manufacturing stage in which a defect is generated, with reference to a distribution, on the wafer, of one or more transistors under measurement whose electrical characteristics do not meet a predetermined standard, and a setting changing section that changes a setting for a manufacturing apparatus that performs a process corresponding to the manufacturing stage in which the defect is generated. | 03-05-2009 |
20090060023 | TRANSMISSION CIRCUIT, CMOS SEMICONDUCTOR DEVICE, AND DESIGN METHOD THEREOF - A transmission circuit, which transmits a differential signal having pulse time larger than a predetermined minimum pulse time, includes: a driving unit for feeding the differential signal as a potential difference between two transmission lines; a driven unit for operating on the basis of the differential signal by receiving the differential signal by the potential difference between the two transmission lines; and a connecting resistor for electrically connecting the two transmission lines. Further, a connecting MOS transistor may be provided near a receiving end of the driven unit. | 03-05-2009 |
20090074420 | MEASURING APPARATUS, TRANSFER CIRCUIT, AND MEASURING METHOD - There is provided a measuring apparatus that measures a characteristic of a transfer circuit transmitting a signal. The transfer circuit includes an electrical signal sending section that transmits a sending signal, a current to light converting section that converts the sending signal into an optical signal, an optical signal transmitting section that transmits the optical signal, a photo-electric converting circuit that converts the optical signal into an electrical signal, a level measuring section that compares the intensity of the electrical signal output from the photo-electric converting circuit and a predetermined reference level to detect a data value of the electrical signal, an electrical signal receiving section that detects a data value of the electrical signal, and a timing controlling section that controls latch timing at which the electrical signal receiving section detects the data value of the electrical signal. The measuring apparatus includes a comparing section that compares the data value of the electrical signal received by the electrical signal receiving section with a predetermined expected value, a setting controlling section that sequentially changes the reference level and the latch timing, and a result storing section that stores a comparison result by the comparing section for each the reference level and the latch timing. | 03-19-2009 |
20090081819 | METHOD AND APPARATUS FOR MANAGING MANUFACTURING EQUIPMENT, METHOD FOR MANUFACTURING DEVICE THEREBY - Provided is a method for managing manufacturing apparatuses used in a managed production line including a plurality of manufacturing processes for manufacturing an electronic device, each of the apparatuses being used in each of the processes, the method including: acquiring a property of a reference device manufactured in a predetermined reference production line including the manufacturing processes to be performed; performing at least one of the manufacturing processes in the managed production line, performing the other manufacturing processes in the reference production line, and manufacturing a comparison device; measuring a property of the comparison device; comparing the measured properties between the reference and the comparison devices; and judging whether the manufacturing apparatus used in the at least one manufacturing process is defective or not, based on a property difference between the reference and the comparison devices. | 03-26-2009 |
20090103869 | CONNECTING DEVICE, CONNECTING SYSTEM, OPTICAL WAVEGUIDE AND CONNECTING METHOD - There is provided a connecting system including a connecting apparatus that includes (i) a signal transfer path that transfers one of an electrical signal and an optical signal and (ii) a connecting device that connects the signal transfer path to a connection target component in such a manner that a signal is capable of being transferred therebetween, and a connected apparatus that includes the connection target component to be connected to the signal transfer path. Here, the connecting device includes a moving portion that has therein a sealed space. The moving portion moves an end portion of the signal transfer path closer to the connection target component so that the end portion of the signal transfer path is connected to the connection target component in response to an increase in a pressure within the moving portion, and moves the end portion away from the connection target component in response to a decrease in the pressure within the moving portion. | 04-23-2009 |
20090162018 | Hermetically Sealing Member Having Optical Transmission Means, Optoelectronic Apparatus, and Optical Transmission Method - A hermetically sealing member with an optical transmission means transmits an optical signal economically and practically between the inside and the outside of a shielding member covering a printed-circuit board while sustaining the hermetically sealed state certainly. An optoelectronic device and an optical transmission method are also provided. A hermetically sealing member ( | 06-25-2009 |
20090251001 | SEMICONDUCTOR CIRCUIT - A first signal processing circuit performs predetermined signal processing on a first signal to provide a change to a characteristic value thereof, and then outputs a second signal. A second signal processing circuit performs predetermined signal processing on the second signal to provide a change to a characteristic value thereof, and then outputs a third signal. A first and a second switching power supplies respectively supply power supply voltages to the first and second signal processing circuits. An amount of change provided to the characteristic value of the first signal by the first signal processing circuit, and an amount of change provided to the characteristic value of the second signal by the second signal processing circuit, are dependent on the respective power supply voltages. Phases of the first and the second switching power supplies are respectively set such that an error between the amount of change in the characteristic value of the first signal and its target value, and an error between that of the second signal and its target value, are to be canceled out by each other. | 10-08-2009 |
20090295417 | TEST SYSTEM, ELECTRONIC DEVICE, AND TEST APPARATUS - Provided is a test system that tests a device under test, including a plurality of internal test circuits that are provided inside the device under test and that are used for testing an operation circuit of the device under test; a device control section that is electrically connected to the plurality of internal test circuits via a common bus and that controls the plurality of internal test circuits by supplying the common bus with an intra-device control signal corresponding to a received external signal; and a test apparatus that supplies the device control section with the external signal. | 12-03-2009 |
20090302317 | SWITCHING DEVICE AND TESTING APPARATUS - There is provided a switching device that electrically connects or disconnects a first terminal and a second terminal to/from each other. The switching device includes a semiconductor layer, a drain electrode that is formed in the semiconductor layer, where the drain electrode is connected to the first terminal, a source electrode that is formed in the semiconductor layer, where the source electrode is connected to the second terminal, a gate insulator that is formed on the semiconductor layer between the drain electrode and the source electrode, a floating gate that is formed on the gate insulator, where the floating gate retains a charge therein, and a tunnel gate that is formed on the floating gate, the tunnel gate supplying a tunnel current determined by a driving voltage applied thereto to charge or discharge the floating gate. | 12-10-2009 |
20100007366 | TEST EQUIPMENT AND SEMICONDUCTOR DEVICE - An interface circuit is connected to an ATE via a test control bus BUS | 01-14-2010 |
20100049453 | TEST APPARATUS AND MANUFACTURING METHOD - Provided is a test apparatus that tests a device under test, comprising a test signal generating section that generates a test signal to be applied to the device under test; a first driver that is electrically connected to a terminal of the device under test and that supplies the test signal to the terminal of the device under test; a correction signal generating section that generates a correction signal for correcting attenuation of the test signal occurring until the test signal reaches the terminal of the device under test; and a second driver that is electrically connected to the terminal of the device under test and that supplies the correction signal to the terminal of the device under test. | 02-25-2010 |
20100052736 | SIGNAL GENERATING APPARATUS, TEST APPARATUS AND CIRCUIT DEVICE - There is provided a signal generating apparatus for generating an output signal corresponding to pattern data supplied thereto. The signal generating apparatus includes a timing generating section that generates a periodic signal, a shift register section including a plurality of flip-flops in a cascade arrangement through which each piece of data of the pattern data is propagated sequentially in response to the periodic signal, a waveform generating section that generates the output signal whose value varies in accordance with a cycle of the periodic signal, based on data values output from the plurality of flip-flops, and an analog circuit that enhances a predetermined frequency component in a waveform of the output signal generated by the waveform generating section. | 03-04-2010 |
20100060336 | SEMICONDUCTOR CIRCUIT - A first signal processor performs predetermined signal processing on an input signal to provide a change to at least one of the characteristic values thereof. A second signal processor is provided in the subsequent stage of the first signal processor and performs predetermined signal processing on an output signal from the first signal processor to provide a change to a characteristic value thereof. An amount of change provided to the characteristic value of the signal by the second signal processor is dependent on a power supply voltage. An amount of change provided to the characteristic value of the signal by the first signal processor is configured to be adjustable. A control circuit monitors a power supply voltage supplied to the second signal processor and adjusts in accordance with the power supply voltage the amount of change provided to the characteristic value of the signal by the first signal processor. | 03-11-2010 |
20100090737 | CLOCK DATA RECOVERY CIRCUIT AND METHOD - A change-point detection circuit | 04-15-2010 |
20100128538 | DATA RECEIVING CIRCUIT - A variable delay circuit provides an adjustable delay to a strobe signal. An input latch circuit latches each bit data included in internal serial data by a strobe signal delayed by the variable delay circuit. A delay set unit adjusts a delay amount provided to the strobe signal by the variable delay circuit. While a calibration operation is being executed in which a known calibration pattern is inputted as serial data, the delay set unit statistically acquires output latch data of the input latch circuit, and adjusts the delay amount such that probabilities of occurrence of 1 and 0 becomes a predetermined ratio. | 05-27-2010 |
20100164584 | Timing Generator - A delay setting data generator generates delay setting data based on rate data. A variable delay circuit delays the test pattern data by a delay time determined by the delay setting data with reference to a predefined unit amount of delay. First rate data designates the period of the test pattern data with a precision determined by the unit amount of delay. Second rate data designates the period of the test pattern data with a precision higher than that determined by the unit amount of delay. The delay setting data generator outputs a first value and a second value in a time division manner at a ratio determined by the second rate data, the first and second values being determined by the first rate data. | 07-01-2010 |
20100259435 | DELAY CIRCUIT - A delay circuit includes a MOSFET and bias voltage sources. The bias voltage sources apply a voltage difference between the drain and source of the MOSFET. The bias voltage source supplies a source voltage to a source electrode of the MOSFET. The bias voltage source supplies a drain voltage to a drain electrode of the MOSFET. An input signal to be delayed is propagated through the gate of the MOSFET in the gate width direction (y-axis direction). | 10-14-2010 |
20100308839 | ELECTRONIC DEVICE IDENTIFYING METHOD - An electronic device that includes an actual operation circuit that operates during an actual operation of the electronic device, a second test circuit and a third test circuit that operate during a test of the electronic device, and a power supply section. The power supply section, during the actual operation of the electronic device, does not apply a power supply voltage to the second test circuit and applies power supply voltages to the actual operation circuit and the third test circuit. The power supply section, to obtain identification of the electronic device, applies a power supply voltage to the second test circuit. | 12-09-2010 |
20100321127 | TEST APPARATUS FOR DIGITAL MODULATED SIGNAL - A test apparatus includes digital modulators provided in increments of multiple channels. A baseband signal generator performs retiming of data input as a modulation signal for the in-phase (quadrature) component, using a timing signal the timing of which can be adjusted, thereby generating a baseband signal. A driver generates a multi-value digital signal having a level that corresponds to the baseband signal output from the baseband signal generator. A multiplier amplitude-modulates a carrier signal with the multi-value digital signal. An adder sums the output signals of the multipliers. | 12-23-2010 |
20110054827 | TEST APPARATUS AND METHOD FOR MODULATED SIGNAL - A test apparatus tests a modulated signal under test received from a DUT. A cross timing data generating unit generates cross timing data which indicates a timing at which the level of the signal under test crosses each of multiple thresholds. An expected value data generating unit generates timing expected value data which indicates a timing at which an expected value waveform of the signal under test crosses each of the multiple thresholds when the expected value waveform is compared with each of the multiple thresholds. A timing comparison unit compares the cross timing data with the timing expected value data. | 03-03-2011 |
20110057642 | TEST APPARATUS FOR DIGITAL MODULATED SIGNAL - An amplitude expected value data generator generates amplitude expected value data that represents, in increments of sampling points, which of multiple amplitude segments the amplitude of a modulated signal waveform that corresponds to the expected value of data to be output from a device under test belongs to. A demodulator performs sampling of the signal waveform to be tested received from the device under test, and generates judgment data that represents, in increments of sampling points, which of the multiple amplitude segments the amplitude of the signal waveform belongs to. A judgment unit makes a comparison between the amplitude expected value data and the judgment data in increments of sampling points. | 03-10-2011 |
20110057665 | TEST APPARATUS FOR DIGITAL MODULATED SIGNAL - A pattern generator generates test data to be transmitted. An encoding circuit generates amplitude data which represent a modulated signal waveform that corresponds to the test data. The amplitude data are generated in a parallel manner in the form of multiple amplitude data in increments of multiple sampling points set within a predetermined period for cycles of the predetermined period. A data rate setting unit receives the multiple amplitude data in increments of sampling points, latches the amplitude data at corresponding sampling timings, and sequentially outputs the amplitude data thus latched. A multi-level driver receives sequentially input amplitude data, and generates a test signal having a level that corresponds to the value of the amplitude data thus received. | 03-10-2011 |
20110133973 | TIME MEASUREMENT CIRCUIT - A time measurement circuit measures the time difference between edges of a first signal and a second signal. A sampling circuit acquires the logical level of the first signal at a timing of the edge of the second signal. When a sampling circuit enters a metastable state, an output signal thereof transits with a long time scale. A transition time measurement circuit measures a transition time (settling time) of the output signal of the sampling circuit in the metastable state. | 06-09-2011 |
20110172957 | TEST APPARATUS AND TEST METHOD - A first transform unit transforms clock change point information which indicates the change timing of a clock signal into information with respect to the frequency domain thereof so as to generate first clock change point frequency information. A digital filter performs filtering of the first clock change point frequency information so as to generate second clock change point frequency information. A second transform unit inverse-transforms the second clock change point frequency information into information with respect to the time domain so as to generate second clock change point information. A judgment unit evaluates a DUT based upon difference data between the change timing represented by the data change point information and the change timing represented by the second clock change point information in increments of phases. | 07-14-2011 |
20110181308 | TEST APPARATUS AND TESTING METHOD - A main power supply supplies a power supply voltage to a power supply terminal of a DUT. A control pattern generator generates a control pattern including a pulse sequence. A compensation circuit intermittently injects a compensation current to the power supply terminal of the DUT via a path different from that of the main power supply. A switch is arranged between an output terminal of a voltage source and the power supply terminal of the DUT, and is turned on and off according to the control pattern. | 07-28-2011 |
20110202296 | TEST APPARATUS AND TEST METHOD - A data signal is transmitted synchronously with a clock signal, and contains n phases (n represents an integer of 2 or more) of data for each cycle of the clock signal. A first time to digital converter generates clock change point information which represents the change timing of the clock signal. A second time to digital converter receives a data sequence in increments of cycles of the clock signal, and generates data change point information items which represent the change timing of the data in increments of phases of the data. A calculation unit calculates difference data between the change timing represented by the data change point information and the change point timing represented by the clock change point information in increments of phases. A judgment unit judges a DUT based upon the difference data received from the calculation unit. | 08-18-2011 |
20110309427 | SWITCHING DEVICE AND TESTING APPARATUS - There is provided a switching device that electrically connects or disconnects a first terminal and a second terminal to/from each other. The switching device includes a semiconductor layer, a drain electrode that is formed in the semiconductor layer, where the drain electrode is connected to the first terminal, a source electrode that is formed in the semiconductor layer, where the source electrode is connected to the second terminal, a gate insulator that is formed on the semiconductor layer between the drain electrode and the source electrode, a floating gate that is formed on the gate insulator, where the floating gate retains a charge therein, and a tunnel gate that is formed on the floating gate, the tunnel gate supplying a tunnel current determined by a driving voltage applied thereto to charge or discharge the floating gate. | 12-22-2011 |
20120112783 | TEST APPARATUS - A test apparatus tests a DUT formed on a wafer. A power supply compensation circuit includes source and a sink switches each controlled according to a control signal. When the source or sink switch is turned on, a compensation pulse current is generated, and the compensation pulse current is injected into a power supply terminal of the DUT via a path that differs from that of a main power supply, or is drawn from the power supply current that flows from the main power supply to the DUT via a path that differs from that of the power supply terminal of the DUT. Of components forming the power supply compensation circuit, including the source and sink switches, a part is formed on the wafer. Pads are formed on the wafer in order to apply a signal to such a part of the power supply compensation circuit formed on the wafer. | 05-10-2012 |
20120146416 | TEST APPARATUS - A DUT comprises a notifying circuit configured to generate a notification signal which is used to notify an external circuit of an event that leads to a change in the operating current of the DUT before such an event occurs. A main power supply supplies electric power to a power supply terminal of the DUT. A power supply compensation circuit comprises a switch element which is controlled according to a control signal, and is configured to generate a compensation pulse current according to the on/off state of the switch element. A compensation control circuit receives the notification signal from the DUT, and outputs, to the power supply compensation circuit, a control signal which is used to control the switch element, and which is generated based upon at least the notification signal. | 06-14-2012 |
20120158348 | TIMING GENERATOR - A delay setting data generator generates delay setting data based on rate data. A variable delay circuit delays the test pattern data by a delay time determined by the delay setting data with reference to a predefined unit amount of delay. First rate data designates the period of the test pattern data with a precision determined by the unit amount of delay. Second rate data designates the period of the test pattern data with a precision higher than that determined by the unit amount of delay. The delay setting data generator outputs a first value and a second value in a time division manner at a ratio determined by the second rate data, the first and second values being determined by the first rate data. | 06-21-2012 |
20120319794 | TEST APPARATUS FOR DIGITAL MODULATED SIGNAL - A test apparatus includes digital modulators provided in increments of multiple channels. A baseband signal generator performs retiming of data input as a modulation signal for the in-phase (quadrature) component, using a timing signal the timing of which can be adjusted, thereby generating a baseband signal. A driver generates a multi-value digital signal having a level that corresponds to the baseband signal output from the baseband signal generator. A multiplier amplitude-modulates a carrier signal with the multi-value digital signal. An adder sums the output signals of the multipliers. | 12-20-2012 |
20130147499 | TEST APPARATUS AND TEST METHOD - A pattern generator generates a pattern signal which represents a test signal to be supplied to a DUT. A driver generates a test signal having a level that corresponds to the pattern signal, and outputs the test signal thus generated to the DUT. A voltage modulator changes, in a predetermined voltage range, the voltage level of the test signal output from the driver DR. | 06-13-2013 |