Patent application number | Description | Published |
20080247492 | Signal Receiving Circuit and Signal Input Detection Circuit - In a signal receiving circuit including a plurality of input channels, there are provided N input detection circuits | 10-09-2008 |
20080303567 | DELAY LOCKED LOOP CIRCUIT - A delay element generates a delayed clock signal which transitions with a delay from a rising (or falling) of a reference clock signal by a delay amount determined based on an output of a loop filter. A signal generation circuit generates two signals which complementarily change according to rising and falling of the reference clock signal and a transition of the delayed clock signal. A charge pump circuit performs on the loop filter, according to these two signals, a push (or pull) operation during an interval extending from a rising (or falling) of the reference clock signal to the transition of the delayed clock signal and a pull (or push) operation during an interval extending from the transition of the delayed clock signal to a falling (or rising) of the reference clock signal. | 12-11-2008 |
20080315911 | Receiver circuit - In a receiver circuit that receives data and clock signals through the cables, the number of transitions of a signal obtained based on the data or clock signal is detected by a frequency detection circuit, and when the number of transitions is not more than a predetermined set value, a signal for resetting the operation of a serial-parallel converter circuit included in a data processing unit is output, so as to control the output of received data. Thus, disconnection of the cable can be detected with low power consumption without providing a pull-up resistor and pull-down resistor and noise resistance can be improved. | 12-25-2008 |
20090086852 | DATA RECEIVER DEVICE AND DATA TRANSMISSION/RECEPTION SYSTEM - The data receiver device includes: a bit phase synchronizing circuit ( | 04-02-2009 |
20090106460 | REMOVABLE MEMORY DEVICE, PHASE SYNCHRONIZING METHOD, PHASE SYNCHRONIZING PROGRAM, MEDIUM RECORDING THE SAME, AND HOST TERMINAL - An object of the present invention is to provide a technique to improve the data transmission efficiency which allows correct reception of the data at the same time. A removable memory device that transmits/receives data to and from a host terminal, which includes: a clock reception section | 04-23-2009 |
20090108872 | INTERFACE CIRCUIT THAT CAN SWITCH BETWEEN SINGLE-ENDED TRANSMISSION AND DIFFERENTIAL TRANSMISSION - An object of the present invention is to realize reduction in an area of an output stage driver in an interface circuit that switches between two transmission systems. The interface circuit has two driver circuits and a drive control circuit that can switch between two driving systems that are a voltage driving system and a current driving system. The two driver circuits are connected to a power supply potential via the drive control circuit. Two input signals and inverted logic signals of the input signals are inputted via a selection circuit. According to a control signal inputted into the drive control circuit, the interface circuit switches between the voltage-driving type single-ended transmission system and current driving type differential transmission system. | 04-30-2009 |
20090262876 | PHASE COMPARATOR AND REGULATION CIRCUIT - A phase comparison process in a timing recovery process for high-speed data communication defines a data window and compares the phase of a clock in the window with the phase of an edge of data so as to realize a parallel process, wherein the phase comparison and the process of determining whether a data edge lies within the window are performed in parallel to each other, and the phase comparison result is output only if the data edge lies within the window. With this configuration, it is possible to perform an accurate phase comparison process with no errors without requiring high-precision delay circuits. | 10-22-2009 |
20090290582 | SIGNAL TRANSMISSION METHOD, TRANSMISSION/RECEPTION DEVICE, AND COMMUNICATION SYSTEM - It is an object of the invention to inhibit a drop in the data transmission efficiency due to the transmission of an interrupt signal. The invention provides a signal transmission method that is characterized in that a reception side and a transmission side partition data into a plurality of data fragments and send and receive the plurality of data fragments over at least two transmission lines, in that the transmission side transmits first data fragments of the plurality of data fragments over a first transmission line of the transmission lines, transmits data packets that include header information, a second data fragment that has the same bit length as the first data fragments, and footer information over a second transmission line other than the first transmission line, and transmits the first data fragments and the second data fragments in synchronization, and in that an interrupt signal for controlling the transmission side is transmitted from the reception side to the transmission side in a time slot that is an interval between first data fragments that are adjacent on the first transmission line. | 11-26-2009 |
20100002822 | PHASE COMPARATOR, PHASE COMPARISON DEVICE, AND CLOCK DATA RECOVERY SYSTEM - A comparison period detecting unit ( | 01-07-2010 |
20100239059 | TRANSMISSION METHOD AND TRANSMISSION APPARATUS - A data transmission circuit transmits transmission data to a receiving apparatus. The clock transmission circuit transmits a transmission clock to the receiving apparatus when the transmission data is transmitted by the data transmission circuit. The phase control circuit varies a phase of the transmission clock to a phase different from that of the transmission data after the transmission clock is transmitted from the clock transmission circuit. | 09-23-2010 |
20100245663 | SEMICONDUCTOR INTEGRATED CIRCUIT AND TRANSMITTER APPARATUS HAVING THE SAME - A semiconductor integrated circuit ( | 09-30-2010 |
20100289534 | INTERFACE CIRCUIT THAT CAN SWITCH BETWEEN SINGLE-ENDED TRANSMISSION AND DIFFERENTIAL TRANSMISSION - An object of the present invention is to realize reduction in an area of an output stage driver in an interface circuit that switches between two transmission systems. The interface circuit has two driver circuits and a drive control circuit that can switch between two driving systems that are a voltage driving system and a current driving system. The two driver circuits are connected to a power supply potential via the drive control circuit. Two input signals and inverted logic signals of the input signals are inputted via a selection circuit. According to a control signal inputted into the drive control circuit, the interface circuit switches between the voltage-driving type single-ended transmission system and current driving type differential transmission system. | 11-18-2010 |
20110007043 | VIDEO SIGNAL PROCESSOR CAPABLE OF SUPPRESSING EXCESSIVE HEAT GENERATION, METHOD USING THE SAME, DISPLAY DEVICE AND METHOD USING THE SAME - A video signal processor for processing input video data in accordance with an input clock signal includes: an input section for changing the format of the video data and outputting resultant data; a logic section for decoding the data output from the input section and outputting decoded data; and a frequency detector for detecting that the clock signal has a frequency higher than a given frequency and outputting a result of the detection as a detection signal. When the frequency of the clock signal is higher than the given frequency, operation of at least part of circuits constituting the video signal processor is stopped in accordance with the detection signal. | 01-13-2011 |
20110074465 | DATA COMMUNICATION CIRCUIT, TRANSMISSION APPARATUS, RECEPTION APPARATUS, AND TRANSMISSION/RECEPTION SYSTEM - A driver supplies data signal via a supply node. A voltage-relaxing transistor has a source connected to the supply node of the driver, a drain connected to a signal node connected to a signal line, and a gate to which the voltage at the signal node is applied. | 03-31-2011 |
20110164693 | INTERFACE CIRCUIT - An interface circuit including an LSI ( | 07-07-2011 |
20120140924 | VIDEO INPUT DEVICE AND VIDEO DISPLAY SYSTEM - An input processing circuit decodes a digital video signal selected by an input signal selector. Decryption circuits each decrypt the encryption of a video signal output from the input processing circuit, and generate an authentication key of the encryption. A video signal selector selects and outputs one of the video signals output from the decryption circuits, to a monitor. The decryption circuits each include a pseudo-signal generation circuit which extracts information from the video signal, and based on the extracted information, generates a pseudo-video signal. | 06-07-2012 |
20130342943 | INPUT PROTECTION CIRCUIT - In an input protection circuit, one end of a resistive element of a protection circuit is connected to an intermediate impedance point of a terminating device, which is connected between a pair of external terminals of a low amplitude differential interface circuit. The other end of the resistive element is connected to an anode terminal of a diode element. A cathode terminal of the diode element is connected to a reference potential terminal. As a result, even when one of external terminals of a low-breakdown voltage circuit is erroneously in contact with a signal terminal (i.e., a bus terminal which is always pulled up via a high resistance resistor) of the socket to be pulled up to a high voltage, the elements forming the circuit are greatly protected from deterioration and damages at low costs, while maintaining the quality of transmission signals. | 12-26-2013 |
20140043079 | INTERCHANNEL SKEW ADJUSTMENT CIRCUIT - An interchannel skew adjustment circuit adjusts signal skew between a first channel and a second channel. The circuit includes a phase adjustment circuit configured to receive a signal of the first channel, delay the signal by a discretely variable delay amount, and output a delayed signal; a channel coupling circuit configured to receive the signal output from the phase adjustment circuit and a signal of the second channel, and detect a phase difference between these two signals; and a controller configured to control the delay amount in the phase adjustment circuit based on a result detected by the channel coupling circuit. This interchannel skew adjustment circuit adjusts the interchannel signal skew only at a sender or a receiver, thereby reducing the circuit area and the power consumption. | 02-13-2014 |
20140043084 | SIGNAL ELECTRIC POTENTIAL CONVERSION CIRCUIT - In a signal electric potential conversion circuit, a capacitor has one end receiving an input signal CIN, and the other end connected to a termination node N1. A conversion circuit receives a potential IN of the termination node N1. A connection element is provided between a power supply VDDH and the termination node N1, and an impedance of the connection element is reduced when the potential IN is lower than a first potential. Another connection element is provided between the termination node N1 and a ground power supply, and an impedance of the connection element is reduced when the potential IN is higher than a second potential. | 02-13-2014 |