Patent application number | Description | Published |
20080279006 | SEMICONDUCTOR MEMORY DEVICE AND ELECTRIC POWER SUPPLY METHOD - A semiconductor device includes a first and a second memory cell array each including a plurality of electrically reprogrammable memory cells arranged in the form of a matrix, the first memory cell array having a larger capacity than the second memory cell array; a plurality of word and bit lines connected to the memory cells; a data program and read control section including a plurality of decoders for, when performing data programming, read or erasure with respect to a corresponding memory cell, selecting, and applying a voltage to corresponding word and bit lines; and a power supply circuit for supplying power to the data program and read control section; wherein when the power supply circuit is to supply power to the second memory cell array, an output terminal of the power supply circuit is electrically connected to at least one of the decoders connected to the first memory cell array. | 11-13-2008 |
20080282119 | MEMORY DEVICE AND BUILT IN SELF-TEST METHOD OF THE SAME - A memory device including, a nonvolatile memory which stores a step item, a parameter start address, and a parameter which has an address corresponding to the parameter start address and defines the step item, and a controller which performs, on the nonvolatile memory, a test step corresponding to the step item defined by the parameter, the controller being formed in the same chip as the nonvolatile memory. | 11-13-2008 |
20090273982 | SEMICONDUCTOR MEMORY DEVICE, SEMICONDUCTOR DEVICE, AND DATA WRITE METHOD - A semiconductor memory device includes an output buffer which outputs an enable signal which makes an external memory device operable, an address buffer which generates an address at which data is held in the external memory device, an input buffer which receives the data held at the address from the external memory device, and a write data buffer which holds the data received by the input buffer, and writes the data in a plurality of memory cells at once. Whenever the write data buffer writes data, the input buffer receives, from the external memory, the data having a size which is written in the memory cells at once. | 11-05-2009 |
20090319840 | SEMICONDUCTOR MEMORY DEVICE AND TEST METHOD THEREOF - A semiconductor memory device includes a nonvolatile memory functioning as a main memory unit, a volatile memory functioning as a buffer unit of the nonvolatile memory, a controller, an ECC buffer, a parity syndrome circuit, an ECC control circuit, a multiplexer, and an ECC error position decoder. | 12-24-2009 |
20110231724 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a NAND flash memory, an input/output unit, a switch, and a controller. The input/output unit includes an ECC unit configured to perform an ECC process on data input to the NAND flash memory, and/or data output from the NAND flash memory, and an interface configured to exchange data with an external apparatus, and controls input/output of data between the NAND flash memory and the external apparatus. The switch is connected to the NAND flash memory and the input/output unit. The controller controls the NAND flash memory and the input/output unit, and switches a connection between the NAND flash memory and the ECC unit, and a connection between the NAND flash memory and the interface via the switch. | 09-22-2011 |
20120063229 | SEMICONDUCTOR MEMORY DEVICE WHICH INCLUDES MEMORY CELL HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE - A semiconductor memory device includes a memory cell array, a power source circuit, a sense amplifier, a control circuit, and a processor. The memory cell array includes a nonvolatile memory cell. The power source circuit includes a first register and generates a voltage. The sense amplifier includes a second register, reads from the memory cell and amplifies the read data. The control circuit includes a third register and controls operations of the power source circuit and the sense amplifier. The processor controls the operations of the power source circuit, the sense amplifier and the control circuit by giving an instruction to the first to third registers. The control circuit decodes the instruction received at the third register so as to control the power source circuit and the sense amplifier directly based on a result of decoding. | 03-15-2012 |
20120072806 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a memory including an array of memory cells. A buffer comprises latches to hold data from the memory cells. The latches constitute latch groups. The latches of each latch group are connected to corresponding one common line through a transfer circuit. An error corrector is connected to the common lines and detects an error bit in received data. A data transfer controller causes the buffer to read out data from memory cells to be verified, repeats reading out of all data in the latches in one latch group to corresponding one of common lines as to-be-verified data segment for different latch groups, and transfers the to-be-verified data segments to the error corrector. A verify controller causes the error corrector to determine whether an error bit is included in to-be-verified data includes the to-be-verified data segments. | 03-22-2012 |
20120155171 | MEMORY SYSTEM - According to one embodiment, a memory system includes a nonvolatile first memory configured to store a boot program, a volatile second memory, a detection circuit configured to detect a level of a power supply voltage, and to generates an interrupt when the power supply voltage becomes less than a first level, and a state machine configured to execute a sequence including a first read operation for reading the boot program from the first memory and a transfer operation for transferring the read boot program to the second memory at power-on. The state machine includes a waiting state for waiting until the interrupt is deactivated when the interrupt is activated during the first read operation or the transfer operation. | 06-21-2012 |
20120155179 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a memory cell array having memory cells, word lines connected to the memory cell array, a generation circuit configured to generate voltages required for operations of the memory cell array, selection circuits connected to the word lines, respectively, each of the selection circuits being configured to select a voltage applied to a word line from the voltages, and a transfer unit configured to transfer items of control data for selecting the voltage to the selection circuits, respectively. The transfer unit includes transfer circuits which shift an enable signal in sequence. The transfer circuits include latch circuits which hold the items of control data based on the shifted enable signal, respectively. | 06-21-2012 |
20120155191 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a first memory configured to receive a first clock and including a first buffer configured to perform a data input operation and a data output operation, a second memory including a second buffer configured to perform a data input operation and a data output operation, and a data bus configured to connect the first buffer and the second buffer. The first memory transfers a second clock to the second memory using the first clock. The first buffer transfers data to the second memory in response to the first clock. The second buffer receives the data from the first buffer in response to the second clock. | 06-21-2012 |
20120206977 | SEMICONDUCTOR MEMORY SYSTEM CAPABLE OF SUPPRESSING CONSUMPTION CURRENT - According to one embodiment, a semiconductor memory system includes a first semiconductor memory device, a second semiconductor memory device, and a wiring line. The wiring line is connected between the first semiconductor memory device and the second semiconductor memory device. When one of the first and second semiconductor memory devices discharges electric charge, the other of the first and second semiconductor memory devices receives the discharged electric charge through the wiring line. | 08-16-2012 |
20120210108 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first sequencer and a second sequencer. The first sequencer operates at a first frequency. The second sequencer operates at a second frequency that is higher than the first frequency. In the first mode, the first sequencer operates in accordance with an instruction received from an external apparatus, and the second sequencer operates under control of the first sequencer. In the second mode, the second sequencer operates in accordance with an instruction received from the external apparatus, and the operation of the first sequencer is stopped. | 08-16-2012 |
20120246422 | SEMICONDUCTOR MEMORY DEVICE WHICH INCLUDES MEMORY CELL HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE - A semiconductor memory device includes a memory cell array, a power source circuit, a sense amplifier, a control circuit, and a processor. The memory cell array includes a nonvolatile memory cell. The power source circuit includes a first register and generates a voltage. The sense amplifier includes a second register, reads from the memory cell and amplifies the read data. The control circuit includes a third register and controls operations of the power source circuit and the sense amplifier. The processor controls the operations of the power source circuit, the sense amplifier and the control circuit by giving an instruction to the first to third registers. The control circuit decodes the instruction received at the third register so as to control the power source circuit and the sense amplifier directly based on a result of decoding. | 09-27-2012 |
20140063941 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes memory cells and memory strings. When lower-page data is first written into a memory string, all memory cells corresponding to the lower-page data are made write-target, a program-verifying level of first ones of the write-targeted memory cells is a first threshold level, and a program-verifying level of second ones of the write-targeted memory cells is a second threshold level. The first threshold level corresponds to data associated with the lowest threshold level and is higher than a third threshold level. The second threshold level is higher than the first threshold level. | 03-06-2014 |
20140063952 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes memory cell arrays each including blocks. The block is unit of erase and includes string-groups. Each string-group includes strings each including a first transistor, memory cell transistors, a second transistor coupled in series. The first transistor is connected to different bit line and the second transistor is connected to same source line. The memory cell arrays are provided with different respective block address signals. The memory cell arrays are provided with different respective string address signals. Each of the block address signals specifies one block. Each of the string address signals specifies one string-group. | 03-06-2014 |
20140071756 | SEMICONDUCTOR MEMORY DEVICE AND CONTROLLER - According to one embodiment, a semiconductor memory device includes a plurality of blocks. The blocks includes a first selection transistor, a second selection transistor, a plurality of memory cell transistors, a first selection gate line and a second selection gate line, and word lines. One of the blocks holds information on a word line, a first selection gate line and/or a second selection gate line including a short-circuiting defect. | 03-13-2014 |
20140369127 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a first string; a second string; and a controller. The first string is coupled with a first bit line and includes first memory cells. The second string is coupled with a second bit line and includes second memory cells. The controller executes writing first data into the first memory cells and writing second data into the second memory cells simultaneously. The controller reads data from the first and second strings after writing the first and second data. | 12-18-2014 |
20150036430 | SEMICONDUCTOR MEMORY DEVICE - A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each string group, a set of memory cell transistors each from each string configures a unit. The controller is configured to: sequentially write, in the first string group, data in first units to which serially-coupled memory cell transistors respectively belong; sequentially write, in the second string group, data in first units to which serially-coupled memory cell transistors respectively belong; and sequentially write, in the first string group, data in second units to which serially-coupled memory cell transistors respectively belong. | 02-05-2015 |
20150036434 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device reads data in units of page. The device includes: a memory cell array; a plurality of latch circuits; and an arithmetic operation circuit. The memory cell array holds data multiplexed in at least three pages. The latch circuits read and hold the multiplexed data at a startup. The arithmetic operation circuit performs operations by use of the multiplexed data. | 02-05-2015 |