Patent application number | Description | Published |
20140231932 | Methods and Apparatus of Metal Gate Transistors - Methods and devices for forming a contact over a metal gate for a transistor are provided. The device may comprise an active area, an isolation area surrounding the active area, and a metal gate above the isolation area, wherein the metal gate comprises a conductive layer. The contact comprises a first contact part within the conductive layer, above the isolation area without vertically overlapping the active area, and a second contact part above the first contact part, connected to the first contact part, and substantially vertically contained within the first contact part. | 08-21-2014 |
20140246709 | SEMICONDUCTOR DEVICE HAVING A SPACER AND A LINER OVERLYING A SIDEWALL OF A GATE STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor device includes a gate structure over a substrate. The device further includes an isolation feature in the substrate and adjacent to an edge of the gate structure. The device also includes a spacer overlying a sidewall of the gate structure. The spacer has a bottom lower than a top surface of the substrate. | 09-04-2014 |
20140252621 | Method For Forming Interconnect Structure - A method for forming interconnect structures comprises forming a metal line made of a first conductive material over a substrate, depositing a dielectric layer over the metal line, patterning the dielectric layer to form an opening, depositing a first barrier layer on a bottom and sidewalls of the opening using an atomic layer deposition technique, depositing a second barrier layer over the first barrier layer, wherein the first barrier layer is coupled to ground and forming a pad made of a second conductive material in the opening. | 09-11-2014 |
20160042992 | Method for Forming Interconnect Structure - A method comprises forming a plurality of interconnect components over a gate structure, wherein a bottom metal line of the interconnect components is connected to the gate structure through a gate plug, depositing a dielectric layer over a top metal line of the interconnect components, forming an opening in the dielectric layer, depositing a first barrier layer on a bottom and sidewalls of the opening using a non-plasma based deposition process, depositing a second barrier layer over the first barrier layer using a plasma based deposition process and forming a pad in the opening. | 02-11-2016 |
Patent application number | Description | Published |
20090115930 | Backlight module and frame thereof - A backlight module and a frame thereof are provided, which comprises an outer frame, an elastic side frame, a connecting arm and a cantilever. Here, the elastic side frame is disposed on the at least one side of the outer frame. The connecting arm is connected to a surface of the elastic side frame. The cantilever is disposed on the connecting arm, and formed a first space with the elastic side frame. The frame of the backlight can protect optical films or panel and sustain optical films against higher stress. | 05-07-2009 |
20100130059 | BACKLIGHT UNIT AND LAMP SOCKET THEREOF - A lamp socket includes a socket body, a flange and a plurality of support members. The flange is connected to the socket body and protrudes from the socket body horizontally. The plurality of support members are connected to the socket body. At least one engaging groove including at least two engaging widths is formed between the plurality of the support members and the flange, so as to secure the socket body to a bezel. | 05-27-2010 |
20100323556 | BACKLIGHT UNIT AND LAMP SOCKET THEREOF - A lamp socket includes a socket body, a flange and a plurality of support members. The flange is connected to the socket body and protrudes from the socket body horizontally. The plurality of support members are connected to the socket body. At least one engaging groove including at least two engaging widths is formed between the plurality of the support members and the flange, so as to secure the socket body to a bezel. | 12-23-2010 |
20120115357 | BACKLIGHT UNIT AND LAMP SOCKET THEREOF - A lamp socket includes a socket body, a flange and a plurality of support members. The flange is connected to the socket body and protrudes from the socket body horizontally. The plurality of support members are connected to the socket body. At least one engaging groove including at least two engaging widths is formed between the plurality of the support members and the flange, so as to secure the socket body to a bezel. | 05-10-2012 |
Patent application number | Description | Published |
20120320099 | PIXEL CIRCUIT AND FLAT DISPLAY PANEL USING THE SAME - An exemplary pixel circuit and a flat display panel using the same are provided. The pixel circuit includes three sub-electrode control circuits. The sub-electrode control circuits are controlled by two scan lines to receive data transmitted from two data lines. One of the three sub-electrode control circuits adjusts stored data by charge sharing. Accordingly, a display control of the pixel circuit is achieved by the three sub-electrode control circuits. | 12-20-2012 |
20130044090 | SUB-PIXEL CIRCUIT, DISPLAY PANEL AND DRIVING METHOD OF FLAT DISPLAY PANEL - A sub-pixel circuit, display panel and driving method of the display panel are provided. The display panel has a plurality of data lines, scan lines and sub-pixel circuits. At least one of the sub-pixel circuits is electrically coupled to one data line and three scan lines. The sub-pixel circuit determines whether to receive data from the coupled data line or not according to scan signals transmitted on the coupled three scan lines, and controls transmittance itself accordingly. Specifically, the scan signals transmitted on the coupled three scan lines are different from each other. | 02-21-2013 |
20140204326 | PIXEL ARRAY SUBSTRATE AND LIQUID CRYSTAL DISPLAY PANEL - A pixel array substrate with new pixel design and a liquid crystal display panel with the pixel array substrate are provided. The pixel array substrate includes a plurality of data lines, a plurality of scan lines and a plurality of pixels. Each of the pixels comprises a first electrode, a first connecting line, a second electrode and a second connecting line. The first electrode is electrically connected with corresponding data line and scan line through the first connecting line, and having a slit. The second pixel is electrically connected with corresponding data line and scan line through the second connecting line. At least a part of the second connecting line is exposed by the slit of the first electrode. | 07-24-2014 |
20150042691 | PIXEL DRIVING METHOD AND LIQUID CRYSTAL DISPLAY IMPLEMENTING THE SAME - A pixel driving method is adapted for a liquid crystal display. Each pixel includes a first sub-pixel and a second sub-pixel, in which the first sub-pixel and the second sub-pixel each includes a first display region and a second display region. The pixel driving method includes providing a first voltage to the first displaying region of the first sub-pixel and the second sub-pixel; providing a second voltage to the second displaying region of the first sub-pixel and a third voltage to the second displaying region of the second sub-pixel; and when the provided first voltage is larger than a predetermined voltage, providing the second voltage so that the provided second voltage is smaller than the provided third voltage. | 02-12-2015 |
20150160518 | ACTIVE DEVICE ARRAY SUBSTRATE - An active device array substrate includes a substrate, a first pixel electrode, and a first raised pattern. The first pixel electrode is disposed on or above the substrate, and the first pixel electrode includes a first truck electrode, a second truck electrode, and a plurality of first branch electrodes. The first truck electrode and the second truck electrode intersect to form a first node at the intersection of the first truck electrode and the second truck electrode. The first branch electrodes are connected to the first truck electrode and the second truck electrode to form a plurality of first domains, wherein the first branch electrodes are asymmetrical with respect to the second truck electrode. The first raised pattern is disposed at least between the first node and the substrate to form a first raised structure at least at the first node. | 06-11-2015 |
Patent application number | Description | Published |
20080246083 | Recessed drift region for HVMOS breakdown improvement - A high-voltage metal-oxide-semiconductor (HVMOS) device having increased breakdown voltage and methods for forming the same are provided. The HVMOS device includes a semiconductor substrate; a gate dielectric on a surface of the semiconductor substrate; a gate electrode on the gate dielectric; a source/drain region adjacent and horizontally spaced apart from the gate electrode; and a recess in the semiconductor substrate and filled with a dielectric material. The recess is between the gate electrode and the source/drain region, and is horizontally spaced apart from the gate electrode. | 10-09-2008 |
20090221118 | High Voltage Semiconductor Devices - A transistor suitable for high-voltage applications and a method of manufacture is provided. A first device is formed by depositing a dielectric layer and a conductive layer over a substrate. A hard mask is deposited over the conductive layer and patterned using photolithography techniques. The photoresist material is removed prior to etching the underlying conductive layer and dielectric layer. The hard mask is also used as an implant mask. Another mask may be deposited and formed over the conductive layer to form other devices in other regions of the substrate. The other mask is preferably removed from over the hard mask prior to etching the conductive layer and the dielectric layer. | 09-03-2009 |
20090273029 | High Voltage LDMOS Transistor and Method - An LDMOS transistor structure and methods of making the same are provided. The structure includes a gate electrode extended on an upper boundary of an extension dielectric region that separates the gate electrode from the drain region of the LDMOS transistor. Moreover, at an area close to an edge of the extended gate electrode portion, the gate electrode further projects downwards into a convex-shaped recess or groove in the upper boundary of the extension dielectric region, forming a tongue. LDMOS transistors with this structure may provide improved suppression of hot carrier effects. | 11-05-2009 |
20110269283 | High Voltage Transistor with Improved Driving Current - A semiconductor device and its method of manufacture are provided. Embodiments forming an active region in a semiconductor substrate, wherein the active region is bounded by an isolation region; forming a first doped region within the active region; forming a gate electrode over the active region, wherein the gate electrode overlies a portion of the first doped region; forming at least one dielectric layer over sidewalls of the gate electrode; forming a pair of spacers on the dielectric layer; and forming a second doped region substantially within the portion of the first doped region adjacent the one of the spacers and spaced apart from the one of the spacers. | 11-03-2011 |