Patent application number | Description | Published |
20120059501 | Method of making apparatus for computing multiple sum of products - A hardware circuit component for executing multiple sum-of-products operations is manufactured as follows. A set of multiplexed sum-of-products functions of a plurality of operands (a, b, c, . . . ), any one of which functions can be selected in dependence upon a select value (sel) by multiplex operations, is received. The sum-of-products functions are then rearranged in a particular manner. The rearranged set of sum-of-products functions is merged into a single merged sum-of-products function containing one or more multiplexing operations. From this a layout design can be generated, and a hardware circuit component such as an integrated circuit manufactured from the layout design. The step of re-arranging the multiple sum-of-products functions comprises aligning the elements of the set of sum-of-products functions in such a manner that the amount of multiplexing in the single merged sum-of-products function is less than in the input set of sum-of-products functions. Additionally, negative terms in the sum-of-products functions are selectively negated so that particular products are always positive. | 03-08-2012 |
20130007085 | Method and Apparatus For Performing Lossy Integer Multiplier Synthesis - A method is provided for deriving an RTL a logic circuit performing a multiplication as the sum of addends operation with a desired rounding position. In this, an error requirement to meet for the design rounding position is derived. For each of the CCT and the VCT implementation a number columns to discard is derived and a constant to include in the sum addends. For an LMS implementation, a number of columns to discard is derived. After discarding the columns and including the constants as appropriate, an RTL representation of the sum of addends operation is derived for each of the CCT, VCT and LMS implementations and a logic circuit synthesized for each of these. The logic circuit which gives the best implementation is selected for manufacture. | 01-03-2013 |
20130103733 | METHOD AND APPARATUS FOR USE IN THE DESIGN AND MANUFACTURE OF INTEGRATED CIRCUITS - A method and apparatus are provided for manufacturing integrated circuits performing invariant integer division x/d. A desired rounding mode is provided and an integer triple (a,b,k) for this rounding mode is derived. Furthermore, a set of conditions for the rounding mode is derived. An RTL representation is then derived using the integer triple. From this a hardware layout can be derived and an integrated circuit manufactured with the derived hardware layout. When the integer triple is derived a minimum value of k for the desired rounding mode and set of conditions is also derived. | 04-25-2013 |
20130152030 | Method and Apparatus for Performing Formal Verification of Polynomial Datapath - A method and apparatus are provided for use in synthesis of RTL integrated circuit design to determine the functional equivalence of designs. For example, the receiver receives a plurality of designs for synthesis in RTL and a data flow graph is derived for each design. Internal bit widths in the data flow graph representations are restricted ( | 06-13-2013 |
20130346927 | METHOD AND APPARATUS FOR SYNTHESISING A SUM OF ADDENDS OPERATION AND AN INTEGRATED CIRCUIT - A method is provided for a synthesising In RTL, a logic circuit and for manufacturing an integrated circuit for performing a sum of addends with faithful rounding. In this, optimisation constraints for a value of bits which may be discarded and a constant to include in a sum of addends are determined ( | 12-26-2013 |
20150178045 | Partially and Fully Parallel Normaliser - Hardware logic arranged to normalise (or renormalise) an n-bit input number is described in which at least a proportion of a left shifting operation is performed in parallel with a leading zero count operation. In various embodiments the left shifting and the leading zero count are performed independently. In various other embodiments, a subset of the bits output by a leading zero counter are input to a left shifter and the output from the left shifter is input to a renormalisation block which completes the remainder of the left shifting operation independently of any further input from the leading zero counter. | 06-25-2015 |
20150205604 | Trailing or Leading Zero Counter Having Parallel and Combinational Logic - A trailing/leading zero counter includes a plurality of hardware logic blocks, each of which calculates one bit of the output value (i.e. the number of trailing/leading zeros depending on whether it is a trailing/leading zero counter). Each hardware logic block includes two blocks of section hardware logic which each receive a section of an input string and generate one or two outputs from this section of bits. Combining logic then combines the outputs of the section hardware logic to generate the bit of the output value. For hardware logic blocks which calculate bits other than the least significant bit of the output, the hardware logic blocks also include one or more OR reduction stages which reduces the length of the input string by pairwise combining of bits using OR gates before the resultant string is divided into two sections and input to the section hardware logic. | 07-23-2015 |
20160070537 | EVALUATION OF POLYNOMIALS WITH FLOATING-POINT COMPONENTS - A Method identifies a floating point implementation of a polynomial that is accurately evaluable. The method comprises determining whether the polynomial has an allowable variety defined by a plurality of sub-varieties, and, if so, partitioning the input domain of the polynomial into a plurality of sub-domains about the sub-varieties. A floating point precision is then identified for each input to the polynomial falling within each sub-domain based on the location of the input within the sub-domain (e.g. how far away the input is from the sub-variety associated with the sub-domain). A floating point implementation for the polynomial is generated so that an input to the polynomial is evaluated using floating point components having the precision identified for the input. | 03-10-2016 |
20160097808 | Implementing Fixed-Point Polynomials in Hardware Logic - A method implements fixed-point polynomials in hardware logic. In an embodiment the method comprises distributing a defined error bound for the whole polynomial between operators in a data-flow graph for the polynomial and optimizing each operator to satisfy the part of the error bound allocated to that operator. The distribution of errors between operators is updated in an iterative process until a stop condition (such as a maximum number of iterations) is reached. | 04-07-2016 |