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Tessariol

Paolo Tessariol, Montebelluna IT

Patent application numberDescriptionPublished
20080266929REFERENCE CELL LAYOUT WITH ENHANCED RTN IMMUNITY - A reference cell layout includes a plurality of active areas, in parallel to each other, and a first contact of the active areas, and a first gate, the first contact shorting the active areas. A memory device includes the reference cell layout and a corresponding array of memory cells having active areas sized substantially identical to the active areas of the reference cell layout and plural second contacts respectively contacting the active areas of the memory cells.10-30-2008
20110248333INTEGRATION OF RESISTORS AND CAPACITORS IN CHARGE TRAP MEMORY DEVICE FABRICATION - A semiconductor device structure and method to form the same. The semiconductor device structure includes a non-volatile charge trap memory device and a resistor or capacitor. A dielectric layer of a charge trap dielectric stack of the memory device is patterned to expose a portion of a first conductive layer peripheral to the memory device. A second conductive layer formed over the dielectric layer and on the exposed portion of the first conductive layer is patterned to form resistor or capacitor contacts and capacitor plates.10-13-2011
20120300546APPARATUS AND METHODS INCLUDING A BIPOLAR JUNCTION TRANSISTOR COUPLED TO A STRING OF MEMORY CELLS - Some embodiments include apparatus and methods having a string of memory cells, a conductive line and a bipolar junction transistor configured to selectively couple the string of memory cells to the conductive line. Other embodiments including additional apparatus and methods are described.11-29-2012
20130043505APPARATUSES AND METHODS COMPRISING A CHANNEL REGION HAVING DIFFERENT MINORITY CARRIER LIFETIMES - Apparatuses, such as memory devices, memory cell strings, and electronic systems, and methods of forming such apparatuses are shown. One such apparatus includes a channel region that has a minority carrier lifetime that is lower at one or more end portions, than in a middle portion. Other apparatuses and methods are also disclosed.02-21-2013
20140048956FORMING ARRAY CONTACTS IN SEMICONDUCTOR MEMORIES - Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.02-20-2014
20140140134APPARATUS AND METHODS INCLUDING A BIPOLAR JUNCTION TRANSISTOR COUPLED TO A STRING OF MEMORY CELLS - Some embodiments include apparatus and methods having a string of memory cells, a conductive line and a bipolar junction transistor configured to selectively couple the string of memory cells to the conductive line. Other embodiments including additional apparatus and methods are described.05-22-2014
20140264447APPARATUSES AND METHODS COMPRISING A CHANNEL REGION HAVING DIFFERENT MINORITY CARRIER LIFETIMES - Apparatuses, such as memory devices, memory cell strings, and electronic systems, and methods of forming such apparatuses are shown. One such apparatus includes a channel region that has a minority carrier lifetime that is lower at one or more end portions, than in a middle portion. Other apparatuses and methods are also disclosed.09-18-2014
20140284812FORMING ARRAY CONTACTS IN SEMICONDUCTOR MEMORIES - Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.09-25-2014

Patent applications by Paolo Tessariol, Montebelluna IT

Paolo Tessariol, Montebelluna (tv) IT

Patent application numberDescriptionPublished
20120119280Charge Trap Non-Volatile Memory - A charge trapping non-volatile memory may be made with a charge trapping medium including a pair of dielectric layers sandwiching a metal or semimetal layer. The metal or semimetal layer may exhibit a lower energy level than either of the adjacent sandwiching charge trapping layers, creating a good electron sink and, in some embodiments, resulting in a thinner charge trapping medium.05-17-2012

Paolo Tessariol, Boise, ID US

Patent application numberDescriptionPublished
20130087849METHOD OF FABRICATING A CHARGE TRAP NAND FLASH MEMORY DEVICE - Subject matter disclosed herein relates to a method of manufacturing a semiconductor integrated circuit device, and more particularly to a method of fabricating a charge trap NAND flash memory device.04-11-2013

Paolo Tessariol, Montevelluna IT

Patent application numberDescriptionPublished
20150262867FORMING ARRAY CONTACTS IN SEMICONDUCTOR MEMORIES - Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.09-17-2015
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