Teh
Bing Mei Teh, Subiaco AU
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20140303727 | DEVICE FOR EAR DRUM REPAIR - A device for use in the repair of an ear drum in a subject in need of such treatment, said device: having a tensile strength Youngs Modulus between approximately 12.5 and 40 MPa; comprising one or more membrane layers, wherein at least one membrane layer comprises a plurality of pores; and wherein the device can support proliferation, migration and/or adhesion of cells selected from the group comprising at least any one or more of: keratinocytes, fibroblasts, vascular cells, mucosal epithelial cells, and stem cells. | 10-09-2014 |
Chee Hak Teh, Gelugor MY
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20110145909 | Interface Logic For A Multi-Core System-On-A-Chip (SoC) - In one embodiment, the present invention includes a system-on-a-chip (SoC) with first and second cores, interface logic coupled to the cores, chipset logic coupled to the interface logic, and a virtual firewall logic coupled between the chipset logic and the second core. The interface logic may include a firewall logic, a bus logic, and a test logic, and the chipset logic may include a memory controller to provide for communication with a memory coupled to the SoC. In some system implementations, both during test operations and functional operations, the second core can be disabled during normal operation to provide for a single core SoC, enabling greater flexibility of use of the SoC in many different implementations. Other embodiments are described and claimed. | 06-16-2011 |
Chee Hak Teh, Penang MY
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20090006165 | Demotion-based arbitration - In one embodiment, the present invention includes a method for arbitrating requests from multiple agents based on an arbitration list to select an agent to receive an arbitration grant, determining whether the selected agent is associated with a grant counter that is at a value of zero, and if so dynamically reordering the arbitration list so that the selected agent is demoted to the lowest portion of the arbitration list. Other embodiments are described and claimed. | 01-01-2009 |
20090172316 | MULTI-LEVEL PAGE-WALK APPARATUS FOR OUT-OF-ORDER MEMORY CONTROLLERS SUPPORTING VIRTUALIZATION TECHNOLOGY - The invention relates generally to computer memory access. Embodiments of the invention provide a multi-level page-walk apparatus and method that enable I/O devices to execute multi-level page-walks with an out-of-order memory controller. In embodiments of the invention, the multi-level page-walk apparatus includes a demotion-based priority grant arbiter, a page-walk tracking queue, a page-walk completion queue, and a command packetizer. | 07-02-2009 |
Chee Hak Teh, Bayan Lepas MY
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20140006737 | PROTECTED ACCESS TO VIRTUAL MEMORY | 01-02-2014 |
20140108695 | INTERFACE LOGIC FOR A MULTI-CORE SYSTEM-ON-A-CHIP (SOC) - In one embodiment, the present invention includes a system-on-a-chip (SoC) with first and second cores, interface logic coupled to the cores, chipset logic coupled to the interface logic, and a virtual firewall logic coupled between the chipset logic and the second core. The interface logic may include a firewall logic, a bus logic, and a test logic, and the chipset logic may include a memory controller to provide for communication with a memory coupled to the SoC. In some system implementations, both during test operations and functional operations, the second core can be disabled during normal operation to provide for a single core SoC, enabling greater flexibility of use of the SoC in many different implementations. Other embodiments are described and claimed. | 04-17-2014 |
Chee Hak Teh, Bayan Lepaz MY
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20130007332 | CONTROLLABLE TRANSACTION SYNCHRONIZATION FOR PERIPHERAL DEVICES - Embodiments of the invention describe a host system capable of associating a PCIe device and another separate device to the same device identifier (e.g., device number). A cycle routing module or logic will identify an I/O transaction involving the device identifier, and route the transaction to one or both of the devices (or, in some instances, identify the I/O transaction as a configuration transaction, and simply update the cycle routing module/logic only). In one embodiment of the invention, a root port of the host system is configured to operate as the above described cycle router. | 01-03-2013 |
Chenghwa Teh, The Rivervale SG
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20080252272 | VOLTAGE REGULATOR WITH COTROL OF SWITCHING ELEMENTS - A regulator comprises an output terminal producing a regulated output voltage, a first comparator, a second comparator, a first sourcing circuit coupled to the output terminal, and a first sinking circuit coupled to the output terminal. The first comparator compares a feedback signal representative of the output voltage and a first sourcing reference signal that is less than a reference signal. The second comparator compares the feedback signal and a first sinking reference signal that is greater than the reference signal. The first sourcing circuit is configured to be responsive to the first comparator by sourcing a first current to the output terminal. The first sinking circuit is configured to be responsive to the second comparator by sinking a second current from the output terminal. | 10-16-2008 |
20110254520 | CONTROLLERS, SYSTEMS AND METHODS FOR IMPLEMENTING MULTI-PHASE CONTROL - A controller includes an input selector, multiple cores and a multiplexer. The multiplexer is operable for multiplexing control signals to multiple output channels to provide multiple output signals. Each output channel can output a respective output signal, and each output signal represents a cyclic rotation of the control signals. The input selector is operable for enabling the cores to operate in a standby state alternately to control a multiplexing sequence of the control signals. | 10-20-2011 |
Cheng Hwa Teh, The Riverdale SG
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20130154592 | CIRCUIT AND METHOD FOR PROVIDING A REFERENCE SIGNAL - An integrated circuit for providing a reference signal to a regulator includes a comparison circuit and a first reference signal adjustor. The comparison circuit is configured to output a control signal based on a difference between levels of a constraint signal of the regulator, such as an input voltage signal or a supply voltage signal, and the reference signal. The regulator has a feedback control loop maintained by the reference signal. The first reference signal adjustor is operatively coupled to the comparison circuit and is configured to adjust the level of the reference signal based on the control signal such that the level of the reference signal increases toward a preset level and does not cause the feedback control loop of the regulator to become saturated when the regulator is in a start-up phase. | 06-20-2013 |
Chenkong Teh, Tokyo JP
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20100315127 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device includes: a first inverter constituted by a first transistor configured to charge a charge point based on an input signal, and a second transistor configured to discharge a discharge point based on the input signal; a P-type third transistor and an N-type fourth transistor with drain-source paths provided in parallel between the charge point and the discharge point; and a second inverter configured to invert a potential of the charge point or the discharge point and supply the inverted potential to gates of the third and fourth transistors, and obtain a delay signal of the input signal from the charge point or the discharge point. The semiconductor integrated circuit device secures a sufficient delay time with a small area. | 12-16-2010 |
20110260754 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device includes: a first inverter constituted by a first transistor configured to charge a charge point based on an input signal, and a second transistor configured to discharge a discharge point based on the input signal; a P-type third transistor and an N-type fourth transistor with drain-source paths provided in parallel between the charge point and the discharge point; and a second inverter configured to invert a potential of the charge point or the discharge point and supply the inverted potential to gates of the third and fourth transistors, and obtain a delay signal of the input signal from the charge point or the discharge point. The semiconductor integrated circuit device secures a sufficient delay time with a small area. | 10-27-2011 |
Chen Kong Teh, Ota Tokyo JP
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20150115925 | A/D CONVERTER AND SEMICONDUCTOR INTEGRATED CIRCUIT - According to one embodiment, an A/D converter includes a first delay cell column in which a plurality of delay cells, to which a first bias current corresponding to a difference voltage between an input voltage and a reference voltage is supplied, is connected in series. The converter includes a second delay cell column in which a plurality of delay cells, to which a second bias current corresponding to a negative-phase difference voltage of the difference voltage is supplied, is connected in series. The converter includes an encoder unit configured to encode a difference value, in delay time of signal propagation, between the first delay cell column and the second delay cell column. | 04-30-2015 |
Chen Kong Teh, Kanagawa JP
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20120119719 | POWER SUPPLY CIRCUIT - According to one embodiment, a power supply circuit includes a switching control unit that compares a DA converted value of the high order bit of a digital compensation value calculated from an output voltage of a smoothing circuit with a detection value of a current flowing into the smoothing circuit and controls the switching of a switching element on the basis of a signal obtained by shifting the timing of the comparison result on the basis of the low order bit of the digital compensation value. | 05-17-2012 |
Chen Kong Teh, Tokyo JP
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20110018584 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit comprises a state holding circuit that inputs an output of one inverter to another inverter with each other; an input circuit that causes a state of the state holding circuit to transition based on a data signal; a first first-conductive transistor that is inserted between an input of the one inverter and an output of the another inverter and is controlled by the data signal; and a first second-conductive transistor that is connected in parallel with the first first-conductive transistor and is controlled by the data signal. | 01-27-2011 |
20130162323 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In a clear period, transistors NT | 06-27-2013 |
20130307585 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit comprises a state holding circuit that inputs an output of one inverter to another inverter with each other; an input circuit that causes a state of the state holding circuit to transition based on a data signal; a first first-conductive transistor that is inserted between an input of the one inverter and an output of the another inverter and is controlled by the data signal; and a first second-conductive transistor that is connected in parallel with the first first-conductive transistor and is controlled by the data signal. | 11-21-2013 |
20140232455 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor chip which includes a first power supply terminal and into which a circuit block which is operated by a power supply voltage supplied to the first power supply terminal is integrated, a power circuit that includes switching transistors and supplies the power supply voltage to the first power supply terminal, and a DCDC control unit that is formed on the first semiconductor chip and generates a control signal for controlling the turning on and off of the switching transistors in response to an information signal from the circuit block and a voltage information signal corresponding to an output voltage from the power circuit. | 08-21-2014 |
20140253066 | POWER CIRCUIT - According to one embodiment, a power circuit includes an input terminal | 09-11-2014 |
20140285172 | POWER CIRCUIT - According to one embodiment, the power circuit includes a first feedback loop which feedbacks information on an output voltage and a second feedback loop which feedbacks information on a load current. When the load current is smaller than a predetermined threshold value, the second feedback loop is blocked and a PWM signal is generated using data of a feedback current signal which is stored before blocking the second feedback loop. | 09-25-2014 |
20150015229 | SEMICONDUCTOR INTEGRATED CIRCUIT - A feedback loop, which feedbacks information of an output voltage or a load current, is provided. The feedback loop has a first mode, which digitalizes and feedbacks the information of the current voltage or the load current, and a second mode, which feedbacks the information as an analog value. | 01-15-2015 |
20150280568 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor chip which includes a first power supply terminal and into which a circuit block which is operated by a power supply voltage supplied to the first power supply terminal is integrated, a power circuit that includes switching transistors and supplies the power supply voltage to the first power supply terminal, and a DCDC control unit that is formed on the first semiconductor chip and generates a control signal for controlling the turning on and off of the switching transistors in response to an information signal from the circuit block and a voltage information signal corresponding to an output voltage from the power circuit. | 10-01-2015 |
E-Jen Teh, Penang MY
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20150151088 | CATHETER ASSEMBLY WITH REUSABLE VALVE - A catheter assembly includes a catheter hub having an elastomeric septum that divides the catheter hub into a distal chamber and a proximal chamber. The septum also includes at least one slit that is closed and sealed when the septum is in an at-rest state. A septum activator is proximal the septum. When an external force pushes the activator against the septum, the activator deforms the septum so as to break the seal and create a flow path through the septum. A portion of the septum activator can be collapsible when subjected to the outside force. When the outside force is removed, the collapsible portion springs back to its at-rest shape, helping to pull the activator out of deforming engagement with the septum so that the septum can reseal. The activator can also be spring-biased away from engagement with the septum so that when the outside force is removed, the spring urges the activator out of engagement with the septum. With the activator removed, the septum slit can reseal. | 06-04-2015 |
20150209550 | CATHETER HAVING DISSOLVABLE PORTIONS AND RELATED METHODS - A catheter has a distal tip having a primary opening formed as the distal opening formed along the axis of the catheter. One or more secondary openings are formed through a side wall of the catheter proximal of the distal opening. A dissolvable portion made up of a resorbable material is disposed within the one or more secondary openings and aligned with the outer surface of the catheter so that the outer surface of the catheter and outer surface of the dissolvable portion combine to present a substantially smooth outer surface. When the catheter distal tip is arranged in a patient's blood vessel, the resorbable material dissolves, so that the fluid delivered by the catheter can exit the catheter through the primary and secondary openings. In some embodiments the secondary openings can be contiguous with the primary opening. | 07-30-2015 |
20150224286 | CATHETER DEVICES WITH SECURING MECHANISMS AND RELATED METHODS - Catheter securement devices are generally described for securing the catheter hub to the access site following successful catheterization. Examples of catheter assemblies with integrated securing mechanisms and related methods are disclosed. The integrated device provides convenience and easy to use access to securing devices that are integrated to the wings of the catheter assemblies. | 08-13-2015 |
Guat Kew Teh, Subang Jaya MY
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20120104583 | SEMICONDUCTOR DEVICE AND METHOD OF PACKAGING SAME - A semiconductor device includes a lead frame that has a die interconnect portion and at least first and second die pads. The die interconnect portion is isolated from the die pads. The device also includes a first die and a second die attached to the first and second die pads and electrically connected to each other by way of the die interconnect portion. The first die is encapsulated in a first medium and the second die is encapsulated in a second medium, the first medium being different from the second medium. | 05-03-2012 |
Gwen Teh, Klang MY
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20140033605 | COMPOSITION TO IMPROVE OXIDATION STABILITY OF FUEL OILS - The present invention describes a composition comprising at least one antioxidant and at least one ethylene vinyl acetate copolymer comprising units being derived from at least one alkyl (meth)acrylate having 1 to 30 carbon atoms in the alkyl residue. The composition is useful as cold flow improver and oxidation stabilizer in fossil fuel oil and or biodiesel fuel oil. | 02-06-2014 |
20150232783 | COMPOSITION TO IMPROVE LOW TEMPERATURE PROPERTIES AND OXIDATION STABILITY OF VEGETABLE OILS AND ANIMAL FATS - The present invention describes a composition comprising: (A) at least one polyalkyl (meth) acrylate polymer having a number average molecular weight M | 08-20-2015 |
Hon Seng Teh, Puchong MY
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20150156197 | SYSTEM AND METHOD FOR TRANSFERRING ELECTRONIC INFORMATION - A system for collecting and transferring electronic information includes one or more servers, having one or more centralized databases for storing or retrieving the data, connected to a network, one or more computing devices connected to the servers via the network for retrieving the data from the centralized databases, and a plurality of biometric devices connected to the servers via the network, located at different locations. Each biometric device comprises a system for identifying users based on biometric data of the users, a system for storing the biometric data and activity information of the users, and a system for sending the biometric data and activity information to the servers, in communication with the servers in real time via the network. | 06-04-2015 |
Huey Fang Teh, Selangor Darul Ehsan MY
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20150299744 | METHODS FOR OBTAINING A GENETICALLY MODIFIED PLANT OR MICROBE AND FOR INCREASING OIL YIELD - Methods are provided for obtaining a genetically modified plant, wherein the plant exhibits an increased oil yield relative to a corresponding control plant that is not so genetically modified. The methods comprise genetically modifying a plant progenitor cell to cause a decrease in triose-phosphate isomerase activity and an increase in glycerol-3-phosphate dehydrogenase activity. The methods also comprise culturing the genetically modified plant progenitor cell to obtain the genetically modified plant. Also provided are methods for increasing oil yield, comprising genetically modifying a plant to cause, in at least one oil-producing organ or tissue of the plant, a decrease in triose-phosphate isomerase activity and an increase in glycerol-3-phosphate dehydrogenase activity. The genetic modification is carried out across more than a single generation. The genetically modified plant exhibits an increased oil yield relative to a corresponding control plant. Also provided are similar methods directed to a microbe. | 10-22-2015 |
Jason Boon Eong Teh, Lumpur MY
Jonathan Teh, Basingstoke GB
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20160004720 | Object-Level Replication of Cloned Objects in a Data Storage System - Object-level replication of cloned objects from a source file system to a target file system in a data storage system maintains relationships between related objects including shared data blocks so that storage requirements in the target file system match storage requirements of the source file system. Specialized processing may be used to scan an indirection object that refers to other file system objects such that objects requiring replication can be identified on an incremental basis based on checkpoint numbers. Checkpoints in the target file system are managed so that checkpoint number requirements for replicated clone objects are enforced in the target file system. | 01-07-2016 |
Jonathan S. Teh, Basingstoke GB
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20080275894 | CONTENT ITEM APPARATUS AND METHOD OF OPERATION THEREFOR - A content item apparatus comprises a content data receiver ( | 11-06-2008 |
20090164572 | APPARATUS AND METHOD FOR CONTENT ITEM ANNOTATION - An apparatus for content item annotation comprises a user group processor ( | 06-25-2009 |
Joo Wooi Teh, Calgary CA
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20080276717 | Method to estimate pent values - The PENT value for a resin may be estimated within ±10% by determining the % of heat flow to melt a fraction of a polymer above or below a set point and comparing it to a graph or algorithm of PENT values related to the % of heat flow to melt entire sample for a number of resins made using the same catalyst system. In a similar manner one may estimate the process conditions to prepare a polymer having a target PENT value based on the conditions used to prepare the samples for the graph or algorithms. The invention provides a simple procedure that may be used at a manufacturing site to estimate PENT values. | 11-13-2008 |
Kheng Shiang Teh, Bayan Lepas MY
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20150086026 | INTRINSICALLY SAFE AUDIO CIRCUIT FOR A PORTABLE TWO-WAY RADIO - An intrinsically safe audio circuit and intrinsically safe portable two-way radio device meet conventional audio output requirements and intrinsically safe design limitations by separating the speaker coil of the device's speaker into separate coils to limit the energy storage possible in any one of the coils. Each separate coil is driven by one of several different audio power amplifiers that each output a substantially identical signal, and each of which are current limited. | 03-26-2015 |
20150280678 | METHOD AND APPARATUS FOR IDENTIFYING AUDIO ACCESSORY THROUGH TWO PIN CONNECTION IN A TWO WAY RADIO - A method and apparatus for detecting the connection of an external audio accessory to an audio device via a two-wire audio jack includes providing a DC bias on the output of the audio circuit connected to the audio jack. The audio jack is such that, when a plug is inserted into the audio jack, the DC bias is removed from an internal routing pin of the audio jack. The change in DC voltage at the internal routing pin indicates connection of the external audio accessory. Furthermore, upon detection, the AC response of the external audio accessory can be determined, and used to select a set of audio settings to be applied to the audio components of the audio device to optimize the performance of the external audio accessory. | 10-01-2015 |
Kheng Shiang Teh, Georgetown MY
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20110136438 | METHOD AND APPARATUS FOR MAINTAINING TRANSMIT AUDIO IN A HALF DUPLEX SYSTEM - A method for maintaining transmit audio quality under harsh environmental conditions, the method includes receiving audio signals into a microphone of a portable communication device and determining at least one parameter associated with the received audio signals. In accordance with an embodiment, the at least one parameter is compared with a received audio parameter threshold. When the at least one parameter falls outside of the received audio parameter threshold, the audio routing is switched from the microphone to the loudspeaker. Subsequent communication may revert back to the microphone or remain at the loudspeaker depending on monitored audio conditions. | 06-09-2011 |
20120134304 | ACOUSTIC PORTING FOR A PORTABLE COMMUNICATION DEVICE - A portable full duplex communication device ( | 05-31-2012 |
Lee Ling Teh, Penang MY
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20120198258 | WIRELESS INPUT DEVICE WITH A POWER SAVING SYSTEM - An input device with a power saving system is provided for reducing the power consumption of the input device when the input device is at rest. The input device may include a sensor, a rest mode switch, control logic and a current controller. The sensor may be configured to obtain an image data in response to a light incident on the sensor. The rest mode switch may be configured to set the input device to various levels of rest modes when it is inactive. The control logic may be coupled to the rest mode switch and the sensor. The control logic may be configured to set the input device to process a portion of the image data on the sensor array during a wake up detection operation when the input device is at rest. The current controller may be coupled to the control logic and the sensor and configured to control the current supply limited to a section of the sensor array containing the portion of image data that is being processed by the input device during the wake up detection operation. | 08-02-2012 |
20150338931 | DRIVING CIRCUIT WITH FAULT DETECTION AND OPTICAL INPUT DEVICE HAVING THE SAME - The present disclosure provides a driving circuit, which includes a switch, a driver unit, a fault detection circuit, and a processor. The switch is coupled between a power terminal and an anode of a light emitting diode (LED) of a light source. The driver unit is coupled between a cathode of the LED and a ground for generating a driving current according to a control signal. The fault detection circuit operatively detects whether the cathode of the LED is shorted and generate a fault signal when detected that the cathode of the LED is shorted. The processor initiates a fault detection period, during which the processor turns off the switch and the driver unit causes the cathode of the LED to be floating while activates the fault detection circuit to detect whether the cathode of the LED is shorted. | 11-26-2015 |
Lee Ling Teh, Bukit Mertajam MY
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20120268032 | COMBINATION LED DRIVER - A driver circuit for a Light Emitting Diode (LED) is disclosed. The driver circuit is capable of supporting a constant LED current circuit configuration as well as an external resistor-controlled LED current circuit configuration. By integrating both configurations into a single driver circuit, the either circuit configuration can be selected without requiring a different driver circuit. | 10-25-2012 |
Ooi Kock Teh, Kajang MY
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20130198904 | BETA-KETOACYL ACP-SYNTHASE II (KASII) GENE FROM JESSENIA BATAUA - The present invention relates to the use of a nucleic acid fragment or part thereof encoding β-ketoacyl ACP synthase II (KASII), particularly which derived from | 08-01-2013 |
Peh Hean Teh, Melaka MY
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20150344730 | PRIMER COMPOSITION, METHOD OF FORMING A PRIMER LAYER ON A SEMICONDUCTOR DEVICE, AND METHOD OF ENCAPSULATING A SEMICONDUCTOR DEVICE - A primer composition is provided. The primer composition includes at least one bi- or multi-functional benzoxazine compound; and at least one compound including a functional group having affinity for a metallic surface, and a cross-linkable group. A method of forming a primer layer on a semiconductor device, and a method of encapsulating a semiconductor device are also provided. | 12-03-2015 |
Poh Huat Teh, Penang MY
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20090051043 | DIE STACKING IN MULTI-DIE STACKS USING DIE SUPPORT MECHANISMS - Systems, methods, and devices that facilitate stacking dies in a multi-die stack using die support mechanisms (DSMs) are presented. DSMs are employed to place a smaller die and attached wires underneath a larger die. DSMs can be placed on each side of the smaller die where the larger die overhangs when placed above the smaller die. The DSMs can be optimally sized to provide support to the larger die to reduce overhang and sagging, while providing a buffer region to protect the smaller die and associated wires. DSMs are employed to facilitate stacking dies that are the same or similar in size by placing a DSM between the dies. The DSM can be optimally sized to provide a buffer region to protect the wires bonded to the top side of the lower die from the upper die, while minimizing overhang to provide support to the upper die. | 02-26-2009 |
Seoh Hian Teh, Taman Damai Impian MY
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20150206829 | SEMICONDUCTOR PACKAGE WITH INTERIOR LEADS - A packaged semiconductor device has a lead frame, a semiconductor die, and bond wires. The lead frame has a two-dimensional array of leads with a subset of interior leads located in the interior of the array that do not extend to the perimeter of the array. The bond wires are connected to the semiconductor die and respective ones of the leads of the array. | 07-23-2015 |
Serene Seoh Hian Teh, Kuala Lumpur MY
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20110115069 | ELECTRONIC DEVICE INCLUDING A PACKAGING SUBSTRATE AND AN ELECTRICAL CONDUCTOR WITHIN A VIA AND A PROCESS OF FORMING THE SAME - An electronic device can include a packaging substrate that including an organic material and a hole extending into the packaging substrate. An electrically conductive member can include a via within the hole, and a lead lying along a major surface of the packaging substrate and electrically connected to the via. In an embodiment, the electrically conductive material can be plated, printed, or otherwise formed within and over the organic material, and a leadframe and a corresponding formation of a molding compound around the leadframe are not necessary. | 05-19-2011 |
Siew Pheng Teh, Ipoh MY
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20110204293 | GOLD CATALYSTS FOR CO OXIDATION AND WATER GAS SHIFT REACTIONS - Methods of making supported monolithic gold (Au) catalysts that can be used for generating a hydrogen-rich gas from gas mixtures containing carbon monoxide, hydrogen and water via a water gas shift reaction, and for the removal of carbon monoxide from air at a low reaction temperature via its oxidation reaction are described. Methods of making highly dispersed gold catalysts on washcoated monoliths and the stabilization of monolithic catalyst supports by the addition of a third metal oxide, such as zirconia (ZrO | 08-25-2011 |
Teik Choon Teh, Jelutong MY
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20130122899 | METHOD AND SYSTEM FOR ROAMING IN A PEER TO PEER NETWORK AMONG RADIO SITES HAVING DYNAMIC REST CHANNEL BASE REPEATER STATIONS - In a peer to peer trunked radio network having a plurality of network locations, each network location includes a plurality of repeaters and a dynamically selected at least temporarily act as a rest channel repeater at each network location. A first repeater at the first network location may determine a first timing at which to broadcast an intra-site beacon and a second timing at which to broadcast an inter-site roaming beacon, the intra-site beacon including at least a rest channel identifier indicating a rest channel of the first network location and the inter-site roaming beacon including at least remote rest channel repeater information identifying a second repeater at a second network location that is currently acting as a rest channel repeater at the second network location. The first repeater may then broadcast the intra-site beacon at the first timing and the inter-site roaming beacon at the second timing. | 05-16-2013 |
Teik Choon Teh, Bagan Serai MY
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20130324177 | METHOD AND APPARATUS FOR AUTOMATICALLY DETERMINING A COMMUNICATION RANGE STATUS OF COMMUNICATING RADIOS - A method is disclosed for determining a connectivity status of radios in a coverage group. Each coverage group includes radios configured to transmit and receive range messages on a channel and a timeslot. Each radio in the coverage group is configured to generate a range message and to transmit the range message to each other radio in the coverage group. Each radio in the coverage group is also configured to receive, from each other radio in the coverage group, a range message generated by each other radio. Based on the range message received from each other radio, each radio is configured to determine bi-directional connectivity between the receiving radio and the radios that sent the D-ARTS messages. The determined bi-directional connectivity status is between each radio and each of at least two other radios in the coverage group. | 12-05-2013 |
Wan Chin Teh, Bayan Lepas MY
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20150039919 | DIRECTED WAKEUP INTO A SECURED SYSTEM ENVIRONMENT - Embodiments of processors, methods, and systems for directed wakeup into a secured system environment are disclosed. In one embodiment, a processor includes a decode unit, a control unit, and a messaging unit. The decode unit is to receive a secured system environment wakeup instruction. The control unit is to cause wake-inhibit indicator to be set for each of a plurality of responding logical processor to be kept in a sleep state. The messaging unit is to send a wakeup message to the plurality of responding logical processors, wherein the wakeup message is to be ignored by each of the plurality of responding logical processors for which the wake-inhibit indicator is set. | 02-05-2015 |