Patent application number | Description | Published |
20120161897 | DIRECTIONAL COUPLER - A directional coupler that has a degree of coupling that is close to constant and is to be used in a predetermined frequency band includes a main line between a first outer electrode and a second outer electrode. A sub-line is provided between a third outer electrode and a fourth outer electrode and is electromagnetically coupled with the main line. A low pass filter is provided between the third outer electrode and the sub-line and has a characteristic in which attenuation increases with increasing frequency in a predetermined frequency band. | 06-28-2012 |
20120319797 | DIRECTIONAL COUPLER - A directional coupler used in a predetermined frequency band includes a main line connected between a first terminal and a second terminal. A first sub line is connected to a third terminal and is electromagnetically coupled to the main line. A second sub line is connected to a fourth terminal and is electromagnetically coupled to the main line. A low pass filter is connected between the first sub line and the second sub line and causes a phase shift to be generated in a passing signal passing therethrough in such a manner that the phase shift monotonically increases within a range from about 0 to about 180 degrees with increasing frequency in the predetermined frequency band. | 12-20-2012 |
20120319800 | ELECTRONIC COMPONENT - An electronic component includes a capacitor having a desired capacitance value and a laminate including a plurality of laminated insulating material layers. Land electrodes are provided on a bottom surface of the laminate. Internal conductors face the land electrodes, respectively, across the insulating material layer within the laminate, have areas larger than those of the land electrodes, respectively, and contain the land electrodes, respectively, when seen in a planar view from a z-axis direction. A capacitor conductor is provided on the positive direction side of the capacitor conductors in the z-axis direction and faces the capacitor conductors. | 12-20-2012 |
20130141184 | DIRECTIONAL COUPLER - In a directional coupler, sub-lines or main lines are electromagnetically coupled to each other to degrade isolation characteristics. A capacitor is located between the sub-lines or between the main lines to cause the isolation characteristics to have poles in order to improve the isolation characteristics of the directional coupler. | 06-06-2013 |
20130241667 | DIRECTIONAL COUPLER - A directional coupler includes in a laminate block, a first main line, a first sub-line, a second sub-line, and a second main line sequentially provided in a lamination direction of layers. Further, each of the first main line, the first sub-line, the second sub-line, and the second main line is divided into at least two divided coil conductors. Furthermore, at least two divided ground conductors are provided between the first sub-line and the second sub-line. | 09-19-2013 |
20130241672 | MULTILAYER BANDPASS FILTER - A multilayer bandpass filter includes a first capacitor electrode of a first stage LC parallel resonator, a second capacitor electrode of a second stage LC parallel resonator, and a third capacitor electrode of a third stage LC parallel resonator. Via electrodes and a line electrode define an inductor electrode of the first stage LC parallel resonator. Via electrodes and a line electrode define an inductor electrode of the second stage LC parallel resonator. Via electrodes and a line electrode define an inductor electrode of the third stage LC parallel resonator. The inductor electrodes of the three LC parallel resonators are arranged so loop planes thereof are disposed about a center axis extending in a stacking direction of dielectric layers. This permits setting of electromagnetic coupling between the LC parallel resonators of an input and an output stage, and allows a filter's attenuation characteristics to be freely set. | 09-19-2013 |
20130300518 | DIRECTIONAL COUPLER - In a directional coupler, a first low pass filter includes a first coil that is connected between a first outer electrode and a main line and has a characteristic in which attenuation increases with increasing frequency in a certain frequency band. A second low pass filter includes a second coil that is connected between a second outer electrode and the main line and has a characteristic in which attenuation increases with increasing frequency in the certain frequency band. A high pass filter is connected, in parallel to the main line, between a point between the first coil and the first outer electrode and a point between the second coil and the second outer electrode and has a characteristic in which attenuation decreases with increasing frequency in the certain frequency band. | 11-14-2013 |
20130342283 | ELECTRONIC COMPONENT - An electronic component includes a capacitor having a desired capacitance value and a laminate including a plurality of laminated insulating material layers. Land electrodes are provided on a bottom surface of the laminate. Internal conductors face the land electrodes, respectively, across the insulating material layer within the laminate, have areas larger than those of the land electrodes, respectively, and contain the land electrodes, respectively, when seen in a planar view from a z-axis direction. A capacitor conductor is provided on the positive direction side of the capacitor conductors in the z-axis direction and faces the capacitor conductors. | 12-26-2013 |
20140098456 | ELECTRONIC COMPONENT - An electronic component includes a capacitor having a desired capacitance value and a laminate including a plurality of laminated insulating material layers. Land electrodes are provided on a bottom surface of the laminate. Internal conductors face the land electrodes, respectively, across the insulating material layer within the laminate, have areas larger than those of the land electrodes, respectively, and contain the land electrodes, respectively, when seen in a planar view from a z-axis direction. A capacitor conductor is provided on the positive direction side of the capacitor conductors in the z-axis direction and faces the capacitor conductors. | 04-10-2014 |
Patent application number | Description | Published |
20080246091 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device capable of suppressing variations in transistor characteristics due to the well proximity effect is provided. Standard cell rows are arranged in a vertical direction, each standard cell row including standard cells arranged in a horizontal direction. In the standard cell rows, positions of the N well and the P region in the vertical direction are switched every other row. Adjacent standard cell rows share the P region or the N well. A distance from a PMOS transistor located at an end of a standard cell row to an end of an N well is greater than or equal to a width of an N well shared by standard cell rows. | 10-09-2008 |
20080246160 | STANDARD CELL AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - This invention prevents a break in a signal wire disposed between wire ends due to attenuation and improves production yields of devices. In a standard cell, a first signal wire extends in a first direction. Second and third signal wires extend in a second direction substantially perpendicular to the first direction and are facing each other across the first signal wire. The second and third signal wires have the widths larger than the width of the first signal wire. | 10-09-2008 |
20090079087 | Semiconductor device and method for fabricating the same - A semiconductor device includes a conductive pattern formed on a substrate, a conductive land formed to come into contact with at least part of the top surface of the conductive pattern, and a conductive section formed on the conductive land. The conductive section is electrically connected through the conductive land to the conductive pattern. | 03-26-2009 |
20110031536 | LAYOUT STRUCTURE OF STANDARD CELL, STANDARD CELL LIBRARY, AND LAYOUT STRUCTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT - In a layout structure of a standard cell including off transistors | 02-10-2011 |
20110073953 | SEMICONDUCTOR INTEGRATED CIRCUIT - A plurality of PMOS transistors are provided on a substrate along an X-axis direction such that a gate length direction of each of the PMOS transistors is parallel to the X-axis direction. A plurality of NMOS transistors are provided on the substrate along the X-axis direction such that a gate length direction of each of the NMOS transistors is parallel to the X-axis direction, and each of the plurality of NMOS transistors is opposed to a corresponding one of the PMOS transistors in the Y-axis direction. Gate lines respectively correspond to the PMOS transistors and the NMOS transistors, and are arranged parallel to each other and extend linearly along the Y-axis direction such that each of the gate lines passes through gate areas of the PMOS transistors and NMOS transistors which correspond to each of the gate lines. | 03-31-2011 |
20110079914 | STANDARD CELL AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - This invention prevents a break in a signal wire disposed between wire ends due to attenuation and improves production yields of devices. In a standard cell, a first signal wire extends in a first direction. Second and third signal wires extend in a second direction substantially perpendicular to the first direction and are facing each other across the first signal wire. The second and third signal wires have the widths larger than the width of the first signal wire. | 04-07-2011 |
20110133253 | SEMICONDUCTOR DEVICE - A layout of a semiconductor device is capable of reliably reducing a variation in gate length due to the optical proximity effect, and enables flexible layout design to be implemented. Gate patterns (G | 06-09-2011 |
20110284964 | SEMICONDUCTOR DEVICE - A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode. | 11-24-2011 |
20110298138 | STANDARD CELL AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - This invention prevents a break in a signal wire disposed between wire ends due to attenuation and improves production yields of devices. In a standard cell, a first signal wire extends in a first direction. Second and third signal wires extend in a second direction substantially perpendicular to the first direction and are facing each other across the first signal wire. The second and third signal wires have the widths larger than the width of the first signal wire. | 12-08-2011 |
20120161241 | SEMICONDUCTOR DEVICE WITH DEVIATION COMPENSATION AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a conductive pattern formed on a substrate, a conductive land formed to come into contact with at least part of the top surface of the conductive pattern, and a conductive section formed on the conductive land. The conductive section is electrically connected through the conductive land to the conductive pattern. | 06-28-2012 |
20120168875 | SEMICONDUCTOR DEVICE - A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained. | 07-05-2012 |
20120292666 | SEMICONDUCTOR DEVICE - In end portions of first and second gate patterns aligned in parallel relation to each other, and opposite end portions of third and fourth gate patterns aligned in parallel relation to each other, the end portion of the first gate pattern extends to be positioned closer to the third and fourth gate patterns than the end portion of the second gate pattern is, and the opposite end portion of the fourth gate pattern extends to be positioned closer to the first and second gate patterns than the opposite end portion of the third gate pattern is. | 11-22-2012 |
20120306101 | SEMICONDUCTOR DEVICE - A power line structure is implemented which is capable of securing large interconnection resources for signal lines while suppressing a power supply voltage drop. Power supply potential lines and substrate potential lines are formed in a first wiring layer, and power supply strap lines are formed in a wiring layer that is located below the center of the overall height of the wiring layers. Upper via portions are arranged at a lower density in the direction in which the power supply strap lines extend than lower via portions. | 12-06-2012 |
20130113112 | SEMICONDUCTOR DEVICE - A local interconnect is formed in contact with an upper surface of an impurity diffusion region and extends to below a potential supply interconnect. A contact hole electrically couples the local interconnect to the potential supply interconnect. The local interconnect, which is formed in contact with the upper surface of the impurity diffusion region, is used for electrically coupling the impurity diffusion region to the potential supply interconnect. | 05-09-2013 |
20130154009 | SEMICONDUCTOR DEVICE - A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode. | 06-20-2013 |
20130234211 | SEMICONDUCTOR DEVICE - A layout of a semiconductor device is capable of reliably reducing a variation in gate length due to the optical proximity effect, and enables flexible layout design to be implemented. Gate patterns (G | 09-12-2013 |
20140077307 | SEMICONDUCTOR DEVICE - A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode. | 03-20-2014 |
20140159160 | SEMICONDUCTOR DEVICE - A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained. | 06-12-2014 |
20140252653 | LAYOUT STRUCTURE OF STANDARD CELL, STANDARD CELL LIBRARY, AND LAYOUT STRUCTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT - In a layout structure of a standard cell including off transistors | 09-11-2014 |
20150014781 | SEMICONDUCTOR DEVICE - A semiconductor device has first conductivity type regions extending in a first direction, and second conductivity type regions extending in the first direction. The first conductivity type regions and the second conductivity type regions are alternately arranged in a second direction perpendicular to the first direction. The semiconductor device includes a first impurity diffused regions formed in the first conductivity type regions, a first local wiring connected to the first conductivity type regions, and extending in the second direction, a first potential supply wiring formed above the first local wiring, and extending in the first direction, and a first contact hole for connecting the first local wiring to the first potential supply wiring. | 01-15-2015 |
20150102420 | SEMICONDUCTOR DEVICE - A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained. | 04-16-2015 |
20150137248 | SEMICONDUCTOR DEVICE - A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode. | 05-21-2015 |
20150303216 | SEMICONDUCTOR DEVICE - A local interconnect is formed in contact with an upper surface of an impurity diffusion region and extends to below a potential supply interconnect. A contact hole electrically couples the local interconnect to the potential supply interconnect. The local interconnect, which is formed in contact with the upper surface of the impurity diffusion region, is used for electrically coupling the impurity diffusion region to the potential supply interconnect. | 10-22-2015 |
Patent application number | Description | Published |
20110242098 | IMAGE PROCESSING APPARATUS, IMAGE PROCESSING METHOD, AND PROGRAM - When a plurality of faces are arranged in order of distance, a three-dimensional effect evaluation value r for each face is determined on the basis of a three-dimensional effect evaluation function Fl having a point A which internally divides the distance from the front side to the rear side in the depth direction at 1:2 as the vertex. A face with the maximum three-dimensional effect evaluation value r, serving as a face with the highest priority, is determined to be a main object. Then, three-dimensional processing is performed on a plurality of images such that the parallax of the determined main object is the minimum, thereby generating an image for three-dimensional display. | 10-06-2011 |
20110243384 | IMAGE PROCESSING APPARATUS AND METHOD AND PROGRAM - There are provided an image processing apparatus, a method, and a program capable of appropriately adjusting the stereoscopic effect in a stereoscopic image with a person. The attention point serving as the provisional cross point position is set to a person's eye, and the cross point position is shifted backwards from the attention point as the percentage of the image occupied by the face increases, thereby adjusting the stereoscopic effect so as to increase an area of the object which is projected forward from the cross point. Regarding the calculation of the back shift amount, the back shift amount is set to increase as the percentage of the face occupied in the standard image increases, and the coefficient is set to be smaller as the number of pixels of the positions nearer than the attention point increases, and the set coefficient kb is multiplied by the back shift amount. | 10-06-2011 |
20130241955 | AUGMENTED REALITY PROVIDING APPARATUS - Provided is an augmented reality providing apparatus capable of preventing an image sickness and reduction of a third party. When a position measurement reliability is less than a first threshold and a movement of HMD | 09-19-2013 |
20140029504 | CONTENTS OPEN SYSTEM, PORTABLE TERMINAL, SERVER, AND NON-TRANSITORY COMPUTER READABLE MEDIUM - When a user A of a terminal a sets to open image data, open data information relating to the image data is transmitted to a server | 01-30-2014 |
20150130828 | IMAGE FILE GENERATION DEVICE AND DISPLAY DEVICE - An image file generation device comprises a first image data acquisition device that acquires N-bit first image data, a second image data generation device that generates M (M05-14-2015 | |
20150332636 | IMAGE DISPLAY DEVICE AND METHOD - An image display method includes the steps of: acquiring a third image formed by applying dynamic range extension processing to a first image and a second image photographed with low sensitivity or low exposure with respect to the first image, or a fourth image without dynamic range extension processing; displaying the acquired image in a transmissive type display panel; and making backlight luminance of a segment corresponding to a high luminance portion in the third image higher than backlight luminance of a segment corresponding to a low luminance portion when the acquired image is determined to be the third image. | 11-19-2015 |
Patent application number | Description | Published |
20090256261 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed. | 10-15-2009 |
20100210107 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and a manufacturing method thereof are provided for the improvement of the reliability of copper damascene wiring in which a film between wiring layers and a film between via layers are comprised of an SiOC film with low dielectric constant. A film between wiring layers, a film between wiring layers, and a film between via layers are respectively comprised of an SiOC film, and stopper insulating films and a cap insulating film are comprised of a laminated film of an SiCN film A and an SiC film B. By doing so, it becomes possible to reduce the leakage current of the film between wiring layers, the film between wiring layers, and the film between via layers, and also possible to improve the adhesion of the film between wiring layers, the film between wiring layers, and the film between via layers to the stopper insulating films and the cap insulating film. | 08-19-2010 |
20110291280 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and a manufacturing method thereof are provided for the improvement of the reliability of copper damascene wiring in which a film between wiring layers and a film between via layers are comprised of an SiOC film with low dielectric constant. A film between wiring layers, a film between wiring layers, and a film between via layers are respectively comprised of an SiOC film, and stopper insulating films and a cap insulating film are comprised of a laminated film of an SiCN film A and an SiC film B. By doing so, it becomes possible to reduce the leakage current of the film between wiring layers, the film between wiring layers, and the film between via layers, and also possible to improve the adhesion of the film between wiring layers, the film between wiring layers, and the film between via layers to the stopper insulating films and the cap insulating film. | 12-01-2011 |
20120015514 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed. | 01-19-2012 |
20130224947 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed. | 08-29-2013 |
20140091468 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed. | 04-03-2014 |
20140312499 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed. | 10-23-2014 |
20150235962 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed. | 08-20-2015 |
Patent application number | Description | Published |
20110210997 | INKJET PRINTHEAD SUBSTRATE, INKJET PRINTHEAD, AND INKJET PRINTING APPARATUS - An inkjet printhead substrate comprises: a pair of individual conductive layers configured to supply electrical power to a heat generation element; a first common conductive layer configured to be connected to one of the pair of individual conductive layers; a second common conductive layer configured to be connected to the other of the pair of individual conductive layers; and an isolation layer configured to be provided between the one of the pair of individual conductive layers and the first common conductive layer, and between the other of the pair of individual conductive layers and the second common conductive layer, wherein the isolation layer is formed from a conductive material which has a lower solubility in ink than a material used for the pairs of individual conductive layers, the first common conductive layer and the second common conductive layer. | 09-01-2011 |
20110221825 | LIQUID DISCHARGE HEAD SUBSTRATE AND LIQUID DISCHARGE HEAD - Performing a high-speed recording operation using a slender liquid discharge head substrate causes an uneven temperature distribution for each energy generating element because the center portion of the liquid discharge head substrate is more liable to accumulate heat than the end portion thereof, which may affect the quality of a recorded image. For this reason, the surface of the energy generating element which contacts liquid is separated into a first region and a second region in which a protection film is thicker than the one in the first region, and the area in the first region for the element positioned at the end portion of the array of the elements is made greater than that in the first region at the center portion thereof. | 09-15-2011 |
20110310183 | SUBSTRATE FOR LIQUID DISCHARGE HEAD AND LIQUID DISCHARGE HEAD - A liquid discharge head includes a heat accumulation layer provided on a board, an energy generation element configured to generate energy to discharge liquid from a discharge port and including a heat generation resistor layer provided on the heat accumulation layer and formed of a material configured to generate heat through supply of electricity and a pair of electrodes connected to the heat generation resistor layer, and an insulation layer including a silicon compound and provided so as to cover the energy generation element, and a line formed of a metal material provided between the heat accumulation layer and the insulation layer, and in at least a portion at a position closer to a flow path than the energy generation element. | 12-22-2011 |
20140022309 | PRINT HEAD AND INK JET PRINTING APPARATUS - A print head and an ink jet printing apparatus are provided which can have smaller sizes if a print head is used which includes a substrate with a plurality of ejection port arrays and a substrate with ejection port arrays longer than the plurality of ejection port arrays. A drive circuit formed in a substrate is formed outside ejection port arrays in the substrate along the extending direction of the ejection port arrays. The drive circuit formed on an overlapping side of the substrate where the ejection port arrays overlap is formed to be longer, along the extending direction of the ejection port arrays, than a drive circuit formed on a side of the substrate which is opposite to the overlapping side. Furthermore, the ejection port arrays and the ejection port arrays overlap in the extending direction of ink supply ports, and the substrates are mounted on a support. | 01-23-2014 |