Tak
Tak Jung, Gwangsan-Gu KR
Patent application number | Description | Published |
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20130193558 | METHOD FOR MANUFACTURING A GROUP III NITRIDE SUBSTRATE USING A CHEMICAL LIFT-OFF PROCESS - The non-polar or semi-polar group III nitride layer disclosed in a specific example of the present invention can be used for substrates for various electronic devices, wherein problems of conventional polar group III nitride substrates are mitigated or solved by using the nitride substrate of the invention, and further the nitride substrate can be manufactured by a chemical lift-off process. | 08-01-2013 |
Tak Lee, Northridge, CA US
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20100052888 | INFORMATION DISPLAY SYSTEMS AND METHODS FOR HYBRID VEHICLES - Information display systems capable of iconically representing the components of a hybrid powertrain and method thereof. In operation, the information display systems indicate the specific powertrain components in the hybrid system that are active in various hybrid operational modes (e.g., electric launch, blended torque, etc.). In particular, active components are highlighted (i.e., increased intensity) by the display and non-active components are faded (i.e., decreased intensity). In one embodiment, the vehicle wheels are depicted with a static intensity in-between that of the active components and the non-active components. This allows the vehicle operator to clearly see which components are active during each hybrid system mode, and to gain a simplified picture of hybrid system behavior during normal operation at a glance. | 03-04-2010 |
Tak Shigihara, Saratoga, CA US
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20120017185 | AUTOMATIC OPTIMAL INTEGRATED CIRCUIT GENERATOR FROM ALGORITHMS AND SPECIFICATION - Systems and methods are disclosed to automatically design a custom integrated circuit includes receiving a specification of the custom integrated circuit including computer readable code and one or more constraints on the custom integrated circuit; automatically devising a processor architecture and generating a processor chip specification uniquely customized to the computer readable code which satisfies the constraints; and synthesizing the chip specification into a layout of the custom integrated circuit. | 01-19-2012 |
20120017187 | AUTOMATIC OPTIMAL INTEGRATED CIRCUIT GENERATOR FROM ALGORITHMS AND SPECIFICATION - Systems and methods are disclosed to automatically design a custom integrated circuit based on algorithmic process or code as input and using highly automated tools that requires virtually no human involvement is disclosed. The method includes receiving a specification of the custom integrated circuit including computer readable code and one or more constraints on the custom integrated circuit; automatically generating a computer architecture for the computer readable code that best fits the constraints; automatically determining an instruction execution sequence based on the code profile and reassigning or delaying the instruction sequence to spread operation over one or more processing blocks to reduce hot spots; continuously evaluating and optimizing one or more factors including physical implementation, and local and global area, timing, or power at an architecture level above RTL or gate-level synthesis; automatically generating a software development kit (SDK) and the associated firmware automatically to execute the computer readable code on the custom integrated circuit; automatically generating associated test suites and vectors for the computer readable code on the custom integrated circuit; and automatically synthesizing the designed architecture and generating a computer readable description of the custom integrated circuit for semiconductor fabrication. | 01-19-2012 |
20130263067 | AUTOMATIC OPTIMAL INTEGRATED CIRCUIT GENERATOR FROM ALGORITHMS AND SPECIFICATION - Systems and methods are disclosed to automatically design a custom integrated circuit by receiving a specification of the custom integrated circuit including computer readable code and one or more constraints on the custom integrated circuit; automatically generating a computer architecture with programmable processor and one or more co-processors for the computer readable code that best fits the constraints; automatically determining an instruction execution sequence based on the code profile and reassigning or delaying the instruction sequence to spread operation over one or more processing blocks to reduce hot spots; automatically generating associated test suites and vectors for the computer readable code on the custom integrated circuit; and automatically synthesizing the designed architecture and generating a computer readable description of the custom integrated circuit for semiconductor fabrication. | 10-03-2013 |