Patent application number | Description | Published |
20130099326 | SEMICONDUCTOR STRUCTURE - A semiconductor structure includes a substrate, a gate structure, and two silicon-containing structures. The substrate includes two recesses defined therein and two doping regions of a first dopant type. Each of the two doping regions extends along a bottom surface and at least portion of a sidewall of a corresponding one of the two recesses. The gate structure is over the substrate and between the two recesses. The two silicon-containing structures are of a second dopant type different from the first dopant type. Each of the two silicon-containing structures fills a corresponding one of the two recesses, and an upper portion of each of the two silicon-containing structures has a dopant concentration higher than that of a lower portion of each of the two silicon-containing structures. | 04-25-2013 |
20130113552 | OFFSET COMPENSATION FOR SENSE AMPLIFIERS - A method of re-offsetting a plurality of amplifier is provided. The method includes testing the plurality of amplifiers based on a re-offset value at bulks of compensation transistors of the plurality of amplifiers; identifying a first group of first amplifiers of the plurality of amplifiers favoring reading a first logic level and/or a second group of second amplifiers of the plurality of amplifiers favoring reading a second logic level different from the first logic level, based on results of the testing step; changing the re-offset value to a new re-offset value; re-offsetting the first group of first amplifiers and/or the second group of second amplifiers based on the new re-offset value; and re-testing the first group of first amplifiers and the second group of second amplifiers. | 05-09-2013 |
20130117164 | METHODS AND SYSTEMS FOR DYNAMIC INVENTORY CONTROL - A production management system is configured to dynamically control inventory of a semiconductor product to prevent overstock and stockout. The production management system includes a production planning module including components containing data of demand forecast, and customer order. The production management system further includes a dynamic inventory control module including a dynamic inventory control simulation module and an inventory management system, wherein the inventory management system is configured to record real inventory data, and wherein the dynamic inventory control simulation module includes simulators for target inventory, future inventory, future shipment and semiconductor product production. | 05-09-2013 |
20130134435 | HIGH ELECTRON MOBILITY TRANSISTOR STRUCTURE WITH IMPROVED BREAKDOWN VOLTAGE PERFORMANCE - A high electron mobility transistor (HEMT) includes a silicon substrate, an unintentionally doped gallium nitride (UID GaN) layer over the silicon substrate. The HEMT further includes a donor-supply layer over the UID GaN layer, a gate structure, a drain, and a source over the donor-supply layer. The HEMT further includes a dielectric layer having one or more dielectric plug portions in the donor-supply layer and top portions between the gate structure and the drain over the donor-supply layer. A method for making the HEMT is also provided. | 05-30-2013 |
20130146224 | ADAPATIVE ENDPOINT METHOD FOR PAD LIFE EFFECT ON CHEMICAL MECHANICAL POLISHING - The present disclosure provides a chemical mechanical polishing (CMP) system. The CMP system includes a pad designed for wafer polishing, a motor driver coupled with the pad and designed to drive the pad during the wafer polishing, and a controller coupled with the motor driver and designed to control the motor driver. The CMP system further includes an in-situ rate monitor designed to collect polishing data from a wafer on the pad, determine CMP endpoint based on a life stage of the pad, and provide the CMP endpoint to the controller. | 06-13-2013 |
20130162332 | INTEGRATED CIRCUITS WITH REDUCED VOLTAGE ACROSS GATE DIELECTRIC AND OPERATING METHODS THEREOF - An integrated circuit includes a first pad configured to carry a signal, a first receiver having an input node, a second receiver having an input node, a first pass gate, and a second pass gate. The first pass gate is coupled between the first pad and the input node of the first receiver. The first pass gate is configured to be turned on when the signal on the first pad is greater than a first voltage level. The second pass gate is coupled between the first pad and the input node of the second receiver. The second pass gate is configured to be turned on when the signal on the first pad is less than a second voltage level. | 06-27-2013 |
20130168810 | INTEGRATED CIRCUITS INCLUDING INDUCTORS - An integrated circuit includes a substrate having a surface and an inductor disposed over the surface of the substrate. The inductor includes a first conductive line disposed over the surface and first conductive structures disposed over and electrically coupled with the first conductive line. The inductor includes second conductive structures disposed over and electrically coupled with the first conductive structures. The inductor includes a second conductive line disposed over and electrically coupled with the second conductive structures. The inductor includes third conductive structures disposed over and electrically coupled with the first conductive line and at least one fourth conductive structure disposed over and electrically coupled with the third conductive structures. The inductor includes a third conductive line disposed over and electrically coupled with the at least one fourth conductive structure, the third conductive line extending substantially parallel to the second conductive line. | 07-04-2013 |
20130181741 | LEVEL SHIFTERS AND INTEGRATED CIRCUITS THEREOF - An integrated circuit including a first level shifter configured to receive a first input signal and a first power supply signal, and to output a first output signal. The integrated circuit further includes a first inverter configured to receive the first output signal, and to output a first inverter signal. The integrated circuit further includes a second level shifter configured to receive a second input signal and a second power supply signal, and to output a second output signal, wherein a voltage level of the second power supply signal is different from a voltage level of the first power supply signal. The integrated circuit further includes a second inverter configure to receive the second output signal, and to output a second inverter signal. The integrated circuit further includes an output buffer configured to receive the first inverter signal and the second inverter signal, and to output a buffer output signal. | 07-18-2013 |
20130182512 | MEMORY CIRCUITS HAVING A PLURALITY OF KEEPERS - A circuit including a memory circuit, the memory circuit includes a first plurality of memory arrays and a first plurality of keepers, each keeper of the first plurality of keepers is electrically coupled with a corresponding one of the first plurality of memory arrays. The memory circuit further includes a first current limiter electrically coupled with and shared by the first plurality of keepers. | 07-18-2013 |
20130188417 | MEMORY CIRCUIT AND METHOD FOR ROUTING THE MEMORY CIRCUIT - A memory circuit includes a first row of memory cells, a first word line and a second word line over and electrically coupled to the first row of memory cells, a second row of memory cells aligned with the first row of memory cells along a predetermined direction, and a third word line and a fourth word line over and electrically coupled to the second row of memory cells. The first word line is aligned with the third word line, and the second word line is aligned with the fourth word line. One of the first word line or the second word line is electrically coupled with one of the third word line or the fourth word line. The other one of the first word line or the second word line is electrically decoupled from the other one of the third word line or fourth word line. | 07-25-2013 |
20130193578 | THROUGH-SILICON VIAS FOR SEMICONDCUTOR SUBSTRATE AND METHOD OF MANUFACTURE - A semiconductor component includes a semiconductor substrate having a top surface. An opening extends from the top surface into the semiconductor substrate. The opening includes an interior surface. A first dielectric liner having a first compressive stress is disposed on the interior surface of the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner. A metal barrier layer is disposed on the third dielectric liner. A conductive material is disposed on the metal barrier layer and fills the opening. | 08-01-2013 |
20130194880 | READING MEMORY DATA - A circuit includes a memory array comprising K number of rows. The circuit further including a reference column. The reference column includes M cells of a first cell type configured to provide a first leakage current, K-M cells of a second cell type different from the first cell type, the K-M cells are configured to provide a second leakage current, and a reference data line connected to the cells of the first cell type and the cells of the second cell type. The circuit further includes a sensing circuit configured to determine a value stored in a memory cell of the memory array based on a voltage of the reference data line. | 08-01-2013 |
20130196458 | METHOD OF TESTING THROUGH SILICON VIAS (TSVS) OF THREE DIMENSIONAL INTEGRATED CIRCUIT (3DIC) - In a method of testing a plurality of through silicon vias (TSVs) chained together by interconnect on a substrate, a test signal is applied to a first test pad among a plurality of test pads, and a return signal is measured at a second test pad among the plurality of test pads. At least one test pad of the plurality of test pads is grounded to the substrate. The remaining test pads of the plurality of test pads are either connected to the plurality of chained TSVs or are grounded. | 08-01-2013 |
20140233330 | WRITE ASSIST CIRCUIT, MEMORY DEVICE AND METHOD - A write assist circuit includes a first switch, a second switch and a bias voltage circuit. The first switch connects a cell supply voltage node of a memory cell to a power supply voltage node in response to a write control signal having a first state, and disconnects the cell supply voltage node from the power supply voltage node in response to the write control signal having a second state. The bias voltage circuit generates, at an output thereof, an adjustable bias voltage lower than the power supply voltage. The second switch connects the cell supply voltage node to the output of the bias voltage circuit in response to the write control signal having the second state, and disconnects the cell supply voltage node from the output of the bias voltage circuit in response to the write control signal having the first state. | 08-21-2014 |