Patent application number | Description | Published |
20080245553 | INTERCONNECTION, ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING AN ELECTRONIC DEVICE - An interconnection includes a bundle of conductive members, each of the conductive members being made of carbon nanotube having an end connected to a first conductive film, and another end connected to a second conductive film separated from the first conductive film; and carbon particles each having a diamond crystal structure, dispersed between the conductive members. | 10-09-2008 |
20110050080 | ELECTRON EMISSION ELEMENT - According to the embodiment, an electron emission element includes a conductive substrate, a first diamond layer of a first conductivity type formed on the conductive substrate, and a second diamond layer of the first conductivity type formed on the first diamond layer. Thereby, it becomes possible to provide the electron emission element having a high electron emission amount and a high current density even in a low electric field at low temperature and the electron emission apparatus using this electron emission element. | 03-03-2011 |
20110057322 | CARBON NANOTUBE INTERCONNECT AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a carbon nanotube interconnect includes a first interconnection layer, an interlayer dielectric film, a second interconnection layer, a contact hole, a plurality of carbon nanotubes and a film. The interlayer dielectric film is formed on the first interconnection layer. The second interconnection layer is formed on the interlayer dielectric film. The contact hole is formed in the interlayer dielectric film between the first interconnection layer and the second interconnection layer. The carbon nanotubes are formed in the contact hole. The carbon nanotubes have a first end connected to the first interconnection layer and a second end connected to the second interconnection layer. The film is formed between the interlayer dielectric film and the second interconnection layer. The film has a portion filled between the second ends of the carbon nanotubes. | 03-10-2011 |
20110233779 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes an interlayer insulation film provided on a substrate including a Cu wiring, a via hole formed in the interlayer insulation film on the Cu wiring, a first metal film selectively formed on the Cu wiring in the via hole, functioning as a barrier to the Cu wiring, and functioning as a promoter of carbon nanotube growth, a second metal film formed at least on the first metal film in the via hole, and functioning as a catalyst of the carbon nanotube growth, and carbon nanotubes buried in the via hole in which the first metal film and the second metal film are formed. | 09-29-2011 |
20110240111 | CARBON NANOTUBE ASSEMBLY, SOLAR CELL, WAVEGUIDE AND SUBSTRATE WITH THE SAME CARBON NANOTUBE ASSEMBLY - According to one embodiment, a carbon nanotube assembly includes a plurality of carbon nanotubes having a length of 10 μm or less in a major axis direction assembled with a space filling rate of 30% or more. | 10-06-2011 |
20120228614 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - According to one embodiment, a semiconductor device is disclosed. The device includes a semiconductor substrate, and an interconnection above the semiconductor substrate. The interconnection includes a co-catalyst layer, a catalyst layer on the co-catalyst layer, and a graphene layer on the catalyst layer. The co-catalyst layer includes a portion contacting the catalyst layer. The portion has a face-centered cubic structure with a (111) plane oriented parallel to a surface of the semiconductor substrate. The catalyst layer has a face-centered cubic structure with a (111) plane oriented parallel to the surface of the semiconductor substrate. | 09-13-2012 |
20120327964 | ALGORITHM TO DRIVE SEMICONDUCTOR LASER DIODE - An algorithm to drive a semiconductor laser diode (LD) is disclosed. The algorithm assumes that the modulation current to keep the extinction ratio in constant has temperature dependence represented by an exponential function under the average output power of the LD is kept constant by an auto-power-control (APC). When a tracking error exists and the approximation by an exponential function is turned out in failure, the algorithm adds a correction to the exponential function determined by a difference between a practically measured modulation current and another modulation current calculated from a value determined for a bared LD. | 12-27-2012 |
20130217226 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a co-catalyst layer and catalyst layer above a surface of a semiconductor substrate. The co-catalyst layer and catalyst layer have fcc structure. The fcc structure is formed such that (111) face of the fcc structure is to be oriented parallel to the surface of the semiconductor substrate. The catalyst includes a portion which contacts the co-catalyst layer. The portion has the fcc structure. An exposed surface of the catalyst layer is planarized by oxidation and reduction treatments. A graphene layer is formed on the catalyst layer. | 08-22-2013 |
20130219697 | METHOD TO PRODUCE OPTICAL TRANSCEIVER - A method to control an optical transceiver, in particular, to drive an LD installed within the optical transceiver is described. The LD in the bias current thereof is determined by the automatic power control (APC) loop to keep an average of the optical output power. The modulation current is determined by a feedback loop to keep the extinction ratio (ER) in a preset range. The initial condition of the modulation current for the feedback loop is set by T-Im characteristic. The T-Im characteristic is first derived based on data measured in a status of the LD not installed in the transceiver. The T-Im characteristic is revised timely by the modulation current practically obtained for the optical transceiver. | 08-29-2013 |
20140231751 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device using multi-layered graphene wires includes a substrate having semiconductor elements formed therein, a first graphene wire formed above the substrate and including a multi-layered graphene layer having a preset impurity doped therein, a second graphene wire formed on the same layer as the first multi-layered graphene wire above the substrate and including a multi-layered graphene layer into which the preset impurity is not doped, a lower-layer contact connected to the undersurface side of the first multi-layered graphene wire, and an upper-layer contact connected to the upper surface side of the second multi-layered graphene wire. | 08-21-2014 |
20150035149 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - According to one embodiment, a semiconductor device includes a semiconductor substrate provided with a lower interconnect layer formed thereon, and having a device region and a mark formation region, a CNT via structure formed in the device region such that it contacts the lower interconnect layer, a first mark formed in the mark formation region, formed by embedding carbon nanotubes, and formed in the same layer as the CNT via structure, a second mark formed in the mark formation region of the semiconductor substrate, formed with no carbon nanotubes, and formed in the same layer as the CNT via structure and the first mark, and an interconnect layer formed on the CNT via structure and the first and second marks, and electrically connected to the CNT via structure. | 02-05-2015 |
20150061131 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device in which CNTs are used for a contact via comprises a substrate includes a contact via groove, a catalyst layer for CNT growth which is formed at the bottom of the groove, and a CNT via formed by filling the CNTs into the groove in which the catalyst layer is formed. Each of the CNTs is formed by stacking a plurality of graphene layers in a state in which they are inclined depthwise with respect to the groove, and formed such that ends of the graphene layers are exposed on a sidewall of the CNT. Further, the CNT is doped with at least one element from the sidewall of the CNT. | 03-05-2015 |
20150061133 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - According to one embodiment, a semiconductor device using a graphene film comprises a catalytic metal layer formed on a groundwork substrate includes a contact via, and a multilayered graphene layer formed in a direction parallel with a surface of the substrate. The catalytic metal layer is formed to be connected to the contact via and covered with an insulation film except one side surface. The multilayered graphene layer is grown from the side surface of the catalytic metal layer which is not covered with the insulation film. | 03-05-2015 |