Patent application number | Description | Published |
20080215171 | Vehicle for recording and reproducing digital data - An apparatus comprising a vehicle and a media player/recorder physically connected with the vehicle, the media player/recorder comprising a wireless receiver to receive a signal representing encoded media data; a storage device to store the encoded media data; a processor comprising a storage controller to retrieve the encoded media data from the storage device, and a digital signal processor to decode the encoded media data retrieved by the storage controller; and an output circuit to output the decoded media data from the processor. | 09-04-2008 |
20080253582 | Vehicle for recording and reproducing digital data - An apparatus includes a vehicle and a media player/recorder physically connected with the vehicle. The media player/recorder includes a wireless receiver to receive a signal representing media data, a storage device to store the media data, a storage controller to retrieve the media data from the storage device, and an output circuit to output the media data. The storage device stores a list of identifiers of desired media selections. The wireless receiver receives a signal representing an identifier of an offered media selection. The storage device stores the offered media selection when the identifier of the offered media selection corresponds to the identifier of one of the desired media selections. | 10-16-2008 |
20080255691 | Apparatus, method, and computer program for recording and reproducing digital data - A media player/recorder includes a wireless receiver to receive a signal representing media data, a storage device to store the media data, a storage controller to retrieve the media data from the storage device, and an output circuit to output the media data. The storage device stores a list of identifiers of desired media selections. The wireless receiver receives a signal representing an identifier of an offered media selection. The storage device stores the offered media selection when the identifier of the offered media selection corresponds to the identifier of one of the desired media selections. | 10-16-2008 |
20110283035 | Hybrid Storage System With Control Module Embedded Solid-State Memory - A hybrid control module includes a host interface control module configured to transfer data to and from a host interface. A first embedded multi-media card (eMMC) interface is configured to (i) connect to a second eMMC interface of a control module embedded solid-state memory (SSM) and (ii) transfer the data between the hybrid control module and the control module embedded SSM. A buffer management module is (i) in communication with the host interface control module, the first eMMC interface and a disk access control module and (ii) configured to buffer the data in volatile memory. The data is received by the buffer management module and from at least one of the host interface control module, the first eMMC interface, or the disk access control module. | 11-17-2011 |
20130097344 | Circuit with memory and support for host accesses of storage drive memory - A circuit including a first memory and a processor. The processor is configured to receive data from a host device and transfer the data from the circuit to a storage drive. The processor is configured to receive the data back from the storage drive when a second memory in the storage drive does not have available space for the data, and prior to the data being transferred from the second memory to a third memory in the storage drive. The processor is configured to: store the data received from the storage drive in the first memory or transfer the data received from the storage drive back to the host device; and based on a request received from the storage drive, transfer the data from the first memory or the host device back to the storage drive. The request indicates that space is available in the second memory for the data. | 04-18-2013 |
20140052887 | APPARATUSES FOR OPERATING, DURING RESPECTIVE POWER MODES, TRANSISTORS OF MULTIPLE PROCESSORS AT CORRESPONDING DUTY CYCLES - A device includes a first processor and a second processor. The first processor is configured to operate in accordance with a first power mode. The first processor includes a first transistor. The first processor is configured to, while operating in accordance with the first power mode, switch the first transistor at a first duty cycle. The second processor is configured to operate in accordance with a second power mode. The second processor includes a second transistor. The second processor is configured to, while operating in accordance with the second power mode, switch the second transistor at a second duty cycle. The second duty cycle is greater than the first duty cycle. The second processor consumes less power while operating in accordance with the second power mode than the first processor consumes while operating in accordance with the first power mode. | 02-20-2014 |
20140071721 | VOLTAGE REGULATOR AND METHOD FOR REGULATING DUAL OUTPUT VOLTAGES BY SELECTIVE CONNECTION BETWEEN A VOLTAGE SUPPLY AND MULTIPLE CAPACITANCES - A voltage regulator including a first, second, and third capacitances, first switches, and second switches. A first terminal of the first capacitance is connected to a first output. The first output is at a first output voltage. A first terminal of the second capacitance is connected to a second output. The second output is at a second output voltage. The first switches connect a first terminal of the third capacitance to a voltage supply, the first output, or the second output. The second switches connect a second terminal of the third capacitance to a reference terminal, the first output, or the second output. The first and second switches are controlled, based on the first output voltage and the second output voltage, to: adjust voltages across the first, second, and third capacitances; maintain the first output at a first predetermined voltage; and maintain the second output at a second predetermined voltage. | 03-13-2014 |
20140325132 | METHOD AND APPARATUS FOR TRANSFERRING DATA BETWEEN A HOST AND BOTH A SOLID-STATE MEMORY AND A MAGNETIC STORAGE DEVICE - A hybrid circuit includes a system-in-a-package (SIP) and an integrated circuit. The SIP includes a solid-state memory, and a first control module. The first control module controls access to the solid-state memory based on a first control signal. The integrated circuit includes an embedded multi-media card (eMMC) module, a second control module, and a management module. The eMMC module is in communication with the SIP according to an eMMC standard. The first eMMC module transfers the first control signal to the first control module to access the solid-state memory. The second control module controls access to a magnetic storage device based on a second control signal. The management module generates the control signals to transfer first data between a host and the SIP via the eMMC module and transfer the first data or second data between the host and the magnetic storage device via the second control module. | 10-30-2014 |
20150113214 | FINAL LEVEL CACHE SYSTEM AND CORRESPONDING METHODS - A data access system including a processor and a final level cache module. The processor is configured to generate a request to access a first physical address. The final level cache module includes a dynamic random access memory (DRAM), a final level cache controller, and a DRAM controller. The final level cache controller is configured to (i) receive the request from the processor, and (ii) convert the first physical address to a first virtual address. The DRAM controller is configured to (i) convert the first virtual address to a second physical address, and (ii) access the DRAM based on the second physical address. | 04-23-2015 |
20150242137 | METHOD AND APPARATUS FOR ACCESSING DATA STORED IN A STORAGE SYSTEM THAT INCLUDES BOTH A FINAL LEVEL OF CACHE AND A MAIN MEMORY - A data access system including a processor having (i) one or more levels of cache, and (ii) a storage system that includes a main memory and a cache module. The cache module includes a controller and a final level of cache to be accessed by the controller prior to accessing the main memory. In response to data required by the processor not being cached within the one or more levels of cache of the processor, the processor generates an address of a physical location within the storage system. The controller converts the address of the physical location within the storage system into an address of a virtual location within the final level of cache. The address of the virtual location is useable by the cache module to determine whether the data required by the processor is cached within the final level of cache. | 08-27-2015 |