Patent application number | Description | Published |
20100019397 | ELECTRICAL CONNECTIONS FOR MULTICHIP MODULES - Conductive lines are formed on a wafer containing multiple circuits. The conductive lines are isolated from the circuits formed within the wafer. Chips are mounted on the wafer and have their chip pads connected to the conductive lines of the wafer. The wafer may then be protected with a packaging resin and singulated | 01-28-2010 |
20110037158 | BALL-GRID-ARRAY PACKAGE, ELECTRONIC SYSTEM AND METHOD OF MANUFACTURE - A multiple-chip-package (MCP) has multiple chip groups and multiple package terminal groups for electrical connections in the MCP. Semiconductor chips of the same chip group are electrically connected to the package terminals of the same package terminal group, while package terminals of different chip groups are electrically connected to the package terminals of different package terminal groups. | 02-17-2011 |
20110156232 | SEMICONDUCTOR MEMORY DEVICE, SEMICONDUCTOR PACKAGE AND SYSTEM HAVING STACK-STRUCTURED SEMICONDUCTOR CHIPS - A module is disclosed. In one embodiment, the module is a memory module including a first multichip package, the first multichip package including a first master chip and a first plurality of slave chips, and a second multichip package, the second multichip package including a second master chip and a second plurality of slave chips. A first through via passes through the first master chip and electrically connects to the first master chip to provide a supply voltage to the first master chip. A second through via passes through the first master chip without being electrically connected to provide a supply voltage to the first master chip. A first set of additional through vias pass through respective ones of the first plurality of slave chips and electrically connect to the respective ones of the first plurality of slave chips, wherein the second through via and first set of additional through vias are aligned to form a first stack of through vias. A third through via passes through the second master chip and electrically connects to the second master chip to provide the supply voltage to the second master chip. A fourth through via passes through the second master chip without being electrically connected to provide a supply voltage to the second master chip. A second set of additional through vias passes through a respective one of the second plurality of slave chips and electrically connects to the respective one of the second plurality of slave chips, wherein the fourth through via and second set of additional through vias are aligned to form a second stack of through vias. A first port is electrically connected to the first and third through vias for providing the supply voltage to the first master chip and the second master chip, and a second port is electrically connected to the first and second stacks of through vias for providing the supply voltage to the first plurality of slave chips and the second plurality of slave chips. | 06-30-2011 |
20110285034 | ELECTRICAL CONNECTIONS FOR MULTICHIP MODULES - Conductive lines are formed on a wafer containing multiple circuits. The conductive lines are isolated from the circuits formed within the wafer. Chips are mounted on the wafer and have their chip pads connected to the conductive lines of the wafer. The wafer may then be protected with a packaging resin and singulated | 11-24-2011 |
20120112359 | Semiconductor Devices and Fabrication Methods thereof - A semiconductor device includes a first semiconductor chip, a first connection structure disposed on a first side of the first semiconductor chip, a second semiconductor chip disposed on a second side of the first semiconductor chip, and a second connection structure disposed between the first and second semiconductor chips, wherein a number of the second connection structures is less than a number of the first connection structures. | 05-10-2012 |
20120235305 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate having a first side and a second side such that the first and second sides face each other, a through via plug penetrating the substrate, an insulating film liner, and an antipollution film. The insulating film liner is between the through via plug and the substrate and the insulating film liner has a recessed surface with respect to the second side. The antipollution film covers the second side and the antipollution film is on the recessed surface and between the through via plug and the substrate. | 09-20-2012 |
20140148007 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate having a first side and a second side such that the first and second sides face each other, a through via plug penetrating the substrate, an insulating film liner, and an antipollution film. The insulating film liner is between the through via plug and the substrate and the insulating film liner has a recessed surface with respect to the second side. The antipollution film covers the second side and the antipollution film is on the recessed surface and between the through via plug and the substrate. | 05-29-2014 |
20140312505 | SEMICONDUCTOR DEVICES AND FABRICATION METHODS THEREOF - A semiconductor device includes a first semiconductor chip, a first connection structure disposed on a first side of the first semiconductor chip, a second semiconductor chip disposed on a second side of the first semiconductor chip, and a second connection structure disposed between the first and second semiconductor chips, wherein a number of the second connection structures is less than a number of the first connection structures. | 10-23-2014 |