Patent application number | Description | Published |
20080285343 | Memory cell programming method and semiconductor device for simultaneously programming a plurality of memory block groups - Provided are a memory cell programming method and a semiconductor device which may be capable of simultaneously writing a bit of data and then another bit of the data to a plurality of memory blocks. The memory programming method, in which M bits of data are written to a plurality of memory blocks, may include a data division operation and a data writing operation where M may be a natural number. In the data division operation, the plurality of memory blocks may be divided into a plurality of memory block groups. In the data writing operation, an i | 11-20-2008 |
20080288849 | Apparatus for generating soft decision values and method thereof - According to an example embodiment, a method of generating a soft decision value using an Analog-to-Digital Converter (ADC) having a given resolution may include receiving metric values calculated based on levels of a transmission signal and output levels of the ADC. Metric values corresponding to a level of a received signal may be selected from among the received metric values. A first maximum metric value may be detected from among the selected metric values when a transmission bit is a first level, and a second maximum metric value may be detected from among the selected metric values when the transmission bit is a second level. The soft decision value may be generated based on a difference between the first maximum metric value and the second maximum metric value. | 11-20-2008 |
20080288853 | Apparatus and method of puncturing of error control codes - A code puncturing apparatus and method is provided. The apparatus includes: a codeword selection unit selecting continuous n−1-number of mother codewords from mother codewords generated from k-bit effective information, where k denotes a natural number, and one redundancy bit; and a puncturing unit selecting k-number of redundancy bits from redundancy bits included in the n−1-number of mother codewords, deleting remaining redundancy bits, and rearranging the n−1-number of mother codewords into an n·k bit-target codeword. Accordingly, a code rate of an Error Control Code (ECC) can be raised. | 11-20-2008 |
20090091990 | Apparatus and method of multi-bit programming - Disclosed are a multi-bit programming apparatus and a multi-bit programming method. The multi-bit programming apparatus may include a first control unit that may generates 2 | 04-09-2009 |
20090103359 | Apparatus and method of multi-bit programming - Multi-bit programming apparatuses and/or methods are provided. A multi-bit programming apparatus may comprise: a multi-bit cell array that includes a first multi-bit cell and a second multi-bit cell; a programming unit for programming first data in the first multi-bit cell, and programming second data in the second multi-bit cell; and a verification unit for verifying whether the first data is programmed in the first multi-bit cell using a first verification voltage, and verifying whether the second data is programmed in the second multi-bit cell using a second verification voltage. The multi-bit programming apparatus may generate better threshold voltage distributions in a multi-bit cell memory. | 04-23-2009 |
20090109748 | Apparatus and method of multi-bit programming - Multi-bit programming apparatuses and/or methods are provided. A multi-bit programming apparatus may include: a first control unit that allocates any one of 2 | 04-30-2009 |
20090122929 | Apparatus and method for cancelling interferences between orthogonal coded signals in mobile communication system - Apparatuses and methods for cancelling interferences between signals are provided. The apparatuses includes: a receiving unit that receives an orthogonal coded signal from a transmitter and generates a received vector; a channel estimation unit that estimates a state of a wireless channel from the transmitter to the apparatus where the cancelling of the interference between signals is performed and generates a channel state matrix; a Q-R decomposition unit that performs Q-R decomposition with respect to the generated channel state matrix and generates a Q matrix and an R matrix, and generates a decision statistic vector based on the generated Q matrix and the received vector; and a signal determination unit that determines a received signal with interference from the orthogonal coded signal being decreased based on the generated decision statistics vector. | 05-14-2009 |
20090150751 | MEMORY SYSTEM THAT USES AN INTERLEAVING SCHEME AND A METHOD THEREOF - A memory system includes a plurality of memory devices, a controller configured to control the plurality of memory devices, and at least one channel connected between the plurality of memory devices and the controller. The at least one channel includes input/output data lines and control signal lines, which are connected with the plurality of memory devices, and chip enable signal lines respectively connected to each of the plurality of memory devices, wherein the chip enable signal lines enable the plurality of memory devices independently. The controller sends a read command or a program command to one of the plurality of memory devices, and while the one of the plurality of memory devices is performing an internal read operation in response to the read command, the controller reads data from another one of the plurality of memory devices, or while the one of the plurality of memory devices is performing an internal program operation in response to the program command, the controller programs data to another one of the plurality of memory devices. | 06-11-2009 |
20090177931 | Memory device and error control codes decoding method - Memory devices and/or error control codes (ECC) decoding methods may be provided. A memory device may include a memory cell array, and a decoder to perform hard decision decoding of first data read from the memory cell array by a first read scheme, and to generate output data and error information of the output data. The memory device may also include and a control unit to determine an error rate of the output data based on the error information, and to determine whether to transmit an additional read command for soft decision decoding to the memory cell array based on the error rate. An ECC decoding time may be reduced through such a memory device. | 07-09-2009 |
20110213930 | Multi-level cell memory device and method thereof - A Multi-Level Cell (MLC) memory device and method thereof are provided. The example MLC memory device may be configured to perform data operations, and may include an MLC memory cell, a first coding device performing a first coding function, the first coding function being one of an encoding function and a decoding function, a second coding device performing a second coding function, the second coding function being one of an encoding function and a decoding function and a signal module configured to perform at least one of instructing the MLC memory cell to store data output by the second coding device if the first and second coding functions are encoding functions, and generating a demapped bit stream based on data retrieved from the MLC memory cell if the first and second coding functions are decoding functions. | 09-01-2011 |