Patent application number | Description | Published |
20110318753 | NEW COMPOUND, PHOSPHORYLATION INHIBITOR, INSULIN RESISTANCE IMPROVING AGENT, PREVENTIVE OR THERAPEUTIC AGENT FOR DIABETES, AND SCREENING METHOD - A new compound inhibiting phosphorylation of Ser727 of STAT3, a phosphorylation inhibitor containing the new compound, an insulin resistance improving agent and a preventive or therapeutic agent for diabetes; and a screening method for at least one of the insulin resistance improving agent and the preventive or therapeutic agent for diabetes. | 12-29-2011 |
20120202969 | COMPOUND, PHOSPHORYLATION INHIBITOR, INSULIN RESISTANCE IMPROVING AGENT, PREVENTIVE OR THERAPEUTIC AGENT FOR DIABETES, AND SCREENING METHOD - A new compound inhibiting phosphorylation of Ser727 of STAT3, a phosphorylation inhibitor containing the new compound, an insulin resistance improving agent and a preventive or therapeutic agent for diabetes; and a screening method for at least one of the insulin resistance improving agent and the preventive or therapeutic agent for diabetes. | 08-09-2012 |
20130022993 | COMPOUND, PHOSPHORYLATION INHIBITOR, INSULIN RESISTANCE IMPROVING AGENT, PREVENTIVE OR THERAPEUTIC AGENT FOR DIABETES, AND SCREENING METHOD - A new compound inhibiting phosphorylation of Ser727 of STAT3, a phosphorylation inhibitor containing the new compound, an insulin resistance improving agent and a preventive or therapeutic agent for diabetes; and a screening method for at least one of the insulin resistance improving agent and the preventive or therapeutic agent for diabetes. | 01-24-2013 |
Patent application number | Description | Published |
20100079212 | SEMICONDUCTOR CIRCUIT APPARATUS AND DELAY DIFFERENCE CALCULATION METHOD - A semiconductor circuit apparatus having a clock oscillating circuit includes a first inverter circuit having a power supply terminal connected to a power supply potential via a first power supply potential connection transistor and a ground terminal connected to a ground potential via a first ground potential connection transistor, an inverter circuit block having a second inverter circuit connected to the power supply potential via a second power supply potential connection transistor and to the ground potential via a second ground potential connection transistor and connected to the first inverter circuit in parallel and a selection circuit block that outputs a power supply potential connection signal to any one of gate terminals of the first and second power supply potential connection transistors and a ground potential connection signal to any one of gate terminals of the first and second ground potential connection transistors. | 04-01-2010 |
20120249230 | INTEGRATED CIRCUIT POWER CONSUMPTION CALCULATING APPARATUS AND PROCESSING METHOD - An integrated circuit power consumption calculating apparatus obtains power consumption of an integrated circuit by outputting circuit component transistor connection information of each of circuit components after setting a group of transistors connected via a source terminal/drain terminal of a transistor within each cell of an integrated circuit, by outputting circuit component logic model information after extracting a logic for each of the circuit components from the circuit component transistor connection information information, by obtaining power information (circuit component power information) of each signal transition state of an input/output terminal for each of the circuit components based on the circuit component transistor connection information information, by generating signal terminal transition information with a logic simulation performed for each of the circuit components of the integrated circuit, and by obtaining power consumption in a signal transition of an input/output terminal of each of the circuit components. | 10-04-2012 |
20120253712 | POWER CONSUMPTION CALCULATION METHOD, POWER CONSUMPTION CALCULATION APPARATUS, AND NON-TRANSITORY COMPUTER-READBLE MEDIUM STORING POWER CONSUMPTION CALCULATION PROGRAM - A method of calculating power consumption of an integrated circuit based on circuit information representing an internal configuration of each circuit and connection-between-circuits information is performed by a computer. The method includes acquiring transition information about input and output signals of the circuit by performing logical analysis, on the assumption of no propagation delay between the circuits, based on input pattern information of the integrated circuit, the connection-between-circuits information, and logical model information about the circuit, extracting from transition patterns of the input signal, a transition pattern causing a glitch in the output signal based on the logical model information, reflecting the glitch in the transition information about the output signal responsive to the input signal having the extracted transition pattern among the acquired transition information, and calculating, by the computer, the power consumption of the integrated circuit based on the transition information in which the glitch is reflected. | 10-04-2012 |
20140289578 | SCAN CIRCUIT HAVING FIRST SCAN FLIP-FLOPS AND SECOND SCAN FLIP-FLOPS - A scan circuit includes first scan flip-flops each including a first logic circuit to receive a plurality of control signals in addition to a scan input signal and a data input signal, and second scan flip-flops each including a second logic circuit to receive the plurality of control signals in addition to a scan input signal and a data input signal, wherein the first scan flip-flops and the second scan flip-flops are connected in series, and the plurality of control signals include only a one-bit reset signal and control signals whose purpose is other than an initialization purpose, and wherein the plurality of control signals are set to a predetermined combination of logic values to cause each of the first scan flip-flops to be initialized to “0” by the first logic circuit and each of the second scan flip-flops to be initialized to “1” by the second logic circuit. | 09-25-2014 |
20140298126 | LATCH CIRCUIT, SCAN TEST CIRCUIT AND LATCH CIRCUIT CONTROL METHOD - A latch circuit includes: a data latch that holds data that has been input according to a first control signal or a second control signal; and a latch controller that includes a first input terminal to which a first operation signal is input, the first operation signal operating the data latch in a first scan method, and a second input terminal to which a second operation signal is input, the second operation signal operating the data latch in a second scan method; wherein when a prescribed value is input to the first input terminal, the latch controller outputs the second control signal to control the data latch, and when a prescribed value is input to the second input terminal, the latch controller outputs the first control signal to control the data latch. | 10-02-2014 |