Steegen
An L. Steegen, Hopewell Junction, NY US
Patent application number | Description | Published |
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20100109048 | METHOD AND STRUCTURE FOR FORMING STRAINED SI FOR CMOS DEVICES - A semiconductor device includes a semiconductor substrate having at least one gap, extending under a portion of the semiconductor substrate. A gate stack is on the semiconductor substrate. A strain layer is formed in at least a portion of the at least one gap. The strain layer is formed only under at least one of a source region and a drain region of the semiconductor device. | 05-06-2010 |
An L. Steegen, Stamford, CT US
Patent application number | Description | Published |
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20080283824 | METHOD AND STRUCTURE FOR FORMING STRAINED SI FOR CMOS DEVICES - A semiconductor device includes a semiconductor substrate having at least one gap, extending under a portion of the semiconductor substrate. A gate stack is on the semiconductor substrate. A strain layer is formed in at least a portion of the at least one gap. The strain layer is formed only under at least one of a source region and a drain region of the semiconductor device. | 11-20-2008 |
An L. Steegen, Stanford, CT US
Patent application number | Description | Published |
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20080254622 | CMOS SILICIDE METAL GATE INTEGRATION - The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure. | 10-16-2008 |