Stanski, US
Charles Stanski, Belvidere, NJ US
Patent application number | Description | Published |
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20090147755 | METHOD AND APPARATUS FOR DATA-CENTRIC MULTIPLEXING - An apparatus and method for data centric multiplexing in a wireless communication system with a plurality of channels comprising assigning a first resource to a first of the plurality of channels; assigning a second resource to a second of the plurality of channels wherein the second resource is not the first resource; assigning a third resource to a third of the plurality of channels wherein the third resource is not the first or the second resource; and assigning a fourth resource to a fourth of the plurality of channels by puncturing at least one of the first, second or third resources and skipping the rest of unpunctured first, second or third resources. | 06-11-2009 |
20090245426 | STORING LOG LIKELIHOOD RATIOS IN INTERLEAVED FORM TO REDUCE HARDWARD MEMORY - An apparatus and method for storing log likelihood ratios in an interleaved form comprising receiving a plurality of interleaved codewords; obtaining at least one log likelihood ratio (LLR) for the plurality of interleaved codewords; storing the at least one LLR in a memory; deinterleaving the plurality of interleaved codewords after the at least one LLR has been stored in the memory; and performing a bit decision of the deinterleaved codewords using the stored at least one LLR. | 10-01-2009 |
20110256902 | OPEN LOOP POWER OFFSET UPDATE - Provided is an feedback mechanism to correct power control information in a broadcast signal that is determined to be incorrect by one or more devices that receive and rely on the broadcast information. A device that receives the incorrect broadcast information can determine a correction and to the information and provide a recommendation to tilt source of the broadcast information. The source can selectively determine whether to modify the broadcast information based on the recommendation from one or more devices. If the broadcast information is modified, subsequent devices that receive the broadcast information are provided with the modified information. If further changes are needed, the subsequent devices can provide further recommended changes. | 10-20-2011 |
Chuck Stanski, Belvidere, NJ US
Patent application number | Description | Published |
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20090011785 | OPEN LOOP POWER OFFSET UPDATE - Provided is an feedback mechanism to correct power control information in a broadcast signal that is determined to be incorrect by one or more devices that receive and rely on the broadcast information. A device that receives the incorrect broadcast information can determine a correction and to the information and provide a recommendation to the source of the broadcast information. The source can selectively determine whether to modify the broadcast information based on the recommendation from one or more devices. If the broadcast information is modified, subsequent devices that receive the broadcast information are provided with the modified information. If further changes are needed, the subsequent devices can provide further recommended changes. | 01-08-2009 |
Stanley B. Stanski, Mount Kisco, NY US
Patent application number | Description | Published |
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20110016326 | Chip Lockout Protection Scheme for Integrated Circuit Devices and Insertion Thereof - A system for implementing a chip lockout protection scheme for an IC device includes an on-chip password register that stores a password externally input by a user; an on-chip security block that generates a chip unlock signal, depending on whether the externally input password matches a correct password; an on-chip false data generator; an input protection scheme configured to gate the external data inputs to functional chip circuitry upon entry of the correct password; and an output protection scheme in communication configured to steer true chip data to external outputs of the IC device upon entry of the correct password, and to steer false data generated by the false data generator to the external outputs upon entry of an incorrect password. The false generated by the false data generator is deterministic and based upon external data inputs, thereby obfuscating whether or not the correct password has been entered. | 01-20-2011 |
Stanley B. Stanski, Essex Junction, VT US
Patent application number | Description | Published |
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20080215945 | System and method for system-on-chip interconnect verification - A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip component, and a comparator coupled to the second linear feedback shift register and the input interface of the second system-on-chip. Another method for verifying includes generating a pseudo-random number sequence with the first linear feedback shift register and the second linear feedback shift register using an identical first initial state, and comparing an output of the first linear feedback shift register with an output of the second linear feedback shift register and reporting a miss-compare. | 09-04-2008 |
20080225431 | Multi-Arm Disk Drive System Having Interleaved Read/Write Operations and Method of Controlling Same - A hard disk drive system that includes one or more rotating data storage platters, a drive controller and multiple actuator assemblies and corresponding respective read/write heads. The actuator assemblies are separately moveable for performing separate data seeks. The controller is configured to interleave the seek and read/write operations of the multiple actuator assemblies and read/write heads with one another. | 09-18-2008 |
20080270965 | METHOD OF REDUCING PEAK POWER CONSUMPTION IN AN INTEGRATED CIRCUIT SYSTEM - A method that utilizes connectivity and/or timing information among a plurality of design partitions of an circuit system to create a clock system that reduces peak power consumption across the system. The method includes sorting the design partitions according to a connectivity model, a timing model, or both, and assigning interleaved clock signals as a function of the design partition ordering. The clock system is created as a function of the interleaved clock signals. | 10-30-2008 |
20090172627 | Design Structure for a Clock System for a Plurality of Functional Blocks - A design structure for a clock system for a plurality of functional blocks designed using a method of reducing peak power that utilizes connectivity and/or timing information among a plurality of design partitions of an integrated circuit system to create a clock system that reduces peak power consumption across the system. The method used to create the design structure includes sorting the design partitions according to a connectivity model, a timing model, or both, and assigning interleaved clock signals as a function of the design partition ordering. The clock system is created as a function of the interleaved clock signals. | 07-02-2009 |