Patent application number | Description | Published |
20080197327 | Wide band gap semiconductor templates - The present invention relates to a thin film structure based on an epitaxial (111)-oriented rare earth-Group IVB oxide on the cubic (001) MgO terminated surface and the ion-beam-assisted deposition (“IBAD”) techniques that are amendable to be over coated by semiconductors with hexagonal crystal structures. The IBAD magnesium oxide (“MgO”) technology, in conjunction with certain template materials, is used to fabricate the desired thin film array. Similarly, IBAD MgO with appropriate template layers can be used for semiconductors with cubic type crystal structures. | 08-21-2008 |
20080234134 | Buffer layers for coated conductors - A composite structure is provided including a base substrate, an IBAD oriented material upon the base substrate, and a cubic metal oxide material selected from the group consisting of rare earth zirconates and rare earth hafnates upon the IBAD oriented material. Additionally, an article is provided including a base substrate, an IBAD oriented material upon the base substrate, a cubic metal oxide material selected from the group consisting of rare earth zirconates and rare earth hafnates upon the IBAD oriented material, and a thick film upon the cubic metal oxide material. Finally, a superconducting article is provided including a base substrate, an IBAD oriented material upon the base substrate, a cubic metal oxide material selected from the group consisting of rare earth zirconates and rare earth hafnates upon the IBAD oriented material, and an yttrium barium copper oxide material upon the cubic metal oxide material. | 09-25-2008 |
20090036313 | Coated superconducting materials - A superconducting article comprising a substrate and a single composite layer deposited onto said substrate, wherein said single composite layer comprises Y | 02-05-2009 |
20090137401 | Chemical Solution Deposition Method of Fabricating Highly Aligned MgO Templates - A superconducting article includes a substrate having an untextured metal surface; an untextured barrier layer of La | 05-28-2009 |
Patent application number | Description | Published |
20090188546 | TERRESTRIAL SOLAR POWER SYSTEM USING III-V SEMICONDUCTOR SOLAR CELLS - A system for generating electrical power from solar radiation utilizing a thin film III-V compound multijunction semiconductor solar cell mounted on a support in a non-planar configuration. | 07-30-2009 |
20090314348 | TERRESTRIAL SOLAR POWER SYSTEM USING III-V SEMICONDUCTOR SOLAR CELLS - A system for generating electrical power from solar radiation utilizing a III-V compound multijunction semiconductor solar cell; a concentrator for focusing sunlight on the solar cell; and a heat spreader connected to the solar cell for cooling the cell. The solar cell is preferably an inverted metamorphic multijunction solar cell. | 12-24-2009 |
20100089440 | Dual Junction InGaP/GaAs Solar Cell - The present application is directed to a multi-terminal semiconductor solar cell. The solar cell may be dual junction solar cells comprising single junctions independently interconnected by a middle lateral conduction layer (MLCL). The solar cells may include a GaAs subcell, a GaInP subcell, and a MLCL disposed therebetween. In addition, the solar cells may include a plurality of terminals. One terminal may be operatively connected to the GaAs subcell, a second terminal may be operatively connected to the GaInP subcell and a third terminal may be operatively connected to the MLCL. | 04-15-2010 |
20150357501 | FOUR JUNCTION INVERTED METAMORPHIC SOLAR CELL - A multijunction solar cell which includes: an upper first solar subcell having a first band gap; a second solar subcell adjacent to said upper first solar subcell and having a second band gap smaller than said first band gap; a third solar subcell adjacent to said second solar subcell and having a third band gap smaller than said second band gap; a graded interlayer adjacent to said third solar subcell, said graded interlayer having a fourth band gap greater than said third band gap; and a lower fourth solar subcell adjacent to said graded interlayer, said lower fourth solar subcell having a fifth band gap smaller than said third band gap such that said lower fourth solar subcell is lattice mismatched with respect to said third solar subcell. | 12-10-2015 |
Patent application number | Description | Published |
20090003040 | Method and System For Encoding to Eliminate Parasitics in Crossbar Array Memories - A method of encoding data stored in a crossbar memory array, such as a nanowire crossbar memory array, to enable significant increases in memory size, modifies data words to have equal numbers of ‘1’ bits and ‘0’ bits, and stores the modified words together with information enabling the original data to be retrieved upon being read out from memory. | 01-01-2009 |
20090174435 | Monolithically-Integrated Graphene-Nano-Ribbon (GNR) Devices, Interconnects and Circuits - The invention discloses new and advantageous uses for carbon/graphene nanoribbons (GNRs), which includes, but is not limited to, electronic components for integrated circuits such as NOT gates, OR gates, AND gates, nano-capacitors, and other transistors. More specifically, the manipulation of the shapes, sizes, patterns, and edges, including doping profiles, of GNRs to optimize their use in various electronic devices is disclosed. | 07-09-2009 |
20130058157 | MAGNETIC RANDOM ACCESS MEMORY DEVICE - The present invention proposes an electronic memory device comprising a memory line including a memory domain. The memory line may contain a number of memory domains and a number of fixed domains, wherein each memory domain stores a single binary bit value. A multiferroic element may be disposed proximate to each memory domain allowing the magnetization of the memory domain to be changed using a spin torque current, and ensuring the stability of the magnetization of the domain when it is not being written. The domain boundary between the memory domain and one of its adjacent fixed domains may thereby be moved. An antiferromagnetic element may be disposed proximate to each fixed domain to ensure the stability of the magnetization of these. The value of each memory domain may be read by applying a voltage to a magnetic tunnel junction comprising the memory domain and measuring the current flowing through it. | 03-07-2013 |
20150370944 | SYSTEM FOR PLACEMENT OPTIMIZATION OF CHIP DESIGN FOR TRANSIENT NOISE CONTROL AND RELATED METHODS THEREOF - Transient voltage noise, including resistive and reactive noise, causes timing errors at runtime. A heuristic framework, Walking Pads, is introduced to minimize transient voltage violations by optimizing power supply pad placement. It is shown that the steady-state optimal design point differs from the transient optimum, and further noise reduction can be achieved with transient optimization. The methodology significantly reduces voltage violations by balancing the average transient voltage noise of the four branches at each pad site. When pad placement is optimized using a representative stressmark, voltage violations are reduced 46-80% across 11 Parsec benchmarks with respect to the results from IR-drop-optimized pad placement. It is shown that the allocation of on-chip decoupling capacitance significantly influences the optimal locations of pads. | 12-24-2015 |
Patent application number | Description | Published |
20100114760 | ONLINE INTERACTIVE ISSUED ACCOUNT ACQUIRED TRANSACTION INFORMATION MANAGEMENT - A single point of access and an integrated user experience for a set of tools are provided for a payment processing system that includes a transaction handler in communication with issuers and acquirers for the processing of payments from the issuers to the acquirers. The tools include: (i) commercial reporting; (ii) expense management; and (iii) account program management tools that are used by (a) issuers who issue the accounts for the cards to account holders and by (b) the account holders. Multiples services are integrated as relevant to specific audiences through an entitlement process, where a single point access is allowed. Applications, which can be developed and/or hosted independently, are accessible through a common interface. | 05-06-2010 |
20100241535 | ACCOUNT ACTIVITY ALERT - An alert recipient receives an account alert after an account activity satisfies criteria of an alert rule. The account alert may be triggered by the usage of a consumer identifier with any of: an application for a new account, an account activation request, or an account usage. To illustrate, a fraudster may utilize the consumer identifier in an application to open a new account, to activate an issued prepaid account, or conduct a transaction on an activated issued prepaid account. Data from the account application, activation, or transaction may be sent to a host that compares the data against the criteria of an alert rule. If the criterion is satisfied, the account alert is sent to the account recipient. The account recipient may required to respond to the alert in order to permit the activity that is the subject of the account alert. | 09-23-2010 |
20110131135 | ONLINE WARRANTY HISTORY STORAGE ACCESS - A message confirming a transaction for the purchase of an item can include identifiers for the item and for a consumer as well as information pertaining to the transaction. The item identifier is used to locate an express warranty for the item. The consumer identifier (e.g.; a number of an account issued to the consumer) is used to locate the consumer's file in which the express warranty is stored along with at least a portion of the information pertaining to the transaction. Other data received in respective messages can be also be stored in the consumer's file. Thereafter, the consumer identifier can be use to retrieve all express warranties stored in the file for past respective purchased items. Information about each express warranty can be compared to the stored portion of the information pertaining to the transaction so as to retrieve only those express warranties that are valid (e.g.; unexpired). | 06-02-2011 |
20120084164 | ACCUMULATION ALERTS - Systems and methods for defining, observing and detecting transactions that initiate an alert message to be sent to one or more users are disclosed. Aggregate threshold, number of transactions and proximity to reward types of alert messages and alert criteria can be defined or selected by users, merchants, and issuers. Alert messages can be sent based on aggregating transaction data from an observed transaction with information from historical transactions, such as credit card transactions. If the aggregated transaction data associated with the transactions match any of the alert criteria, then alert messages can be sent to one or more users. An alert message may include information from the alert trigger as well as the aggregated transaction data. | 04-05-2012 |
Patent application number | Description | Published |
20130305090 | TEST CONFIGURATION RESOURCE MANAGER - A test configuration resource manager and a method of managing test configuration resources in a network test system. A computer readable storage medium may store instructions that, when executed, cause a computing device to receive a user input identifying a portion of a first test configuration, store the identified portion of the first test configuration as a test configuration resource in a library of test configuration resources, receive a user input identifying a stored test configuration resource, retrieve the identified stored test configuration resource, and incorporate the retrieved test configuration resource into a second test configuration. The library of test configuration resources may include one or more of port resources, protocol resources, and traffic resources. | 11-14-2013 |
20130305091 | DRAG AND DROP NETWORK TOPOLOGY EDITOR FOR GENERATING NETWORK TEST CONFIGURATIONS - There is disclosed a method and apparatus for editing test configurations. The method includes displaying a graphical representation of a test configuration to be tested by a test system on a user interface and receiving user input identifying network topology to be added to the test configuration, the network topology including a device group defined by a number of emulated traffic sources, a set of protocols and a number of ports. The method further includes updating the graphical representation of the test configuration to include the network topology; the graphical representation of the network topology including graphical representations of the test system, the emulated traffic sources, the set of protocols, and the number of ports connecting the emulated traffic sources to the test system. | 11-14-2013 |
20140078929 | AUTOMATIC ADDRESS CONFIGURATION IN A NETWORK TEST SYSTEM - A method for managing virtual device addresses and an address manager for a network test system comprising a plurality of ports including a first port. A respective plurality of virtual devices to be emulated by each of the plurality of ports may be defined, each plurality of virtual devices including a respective first virtual device. Addresses may be automatically assigning to each of the virtual devices in accordance with a start value, an intraport pattern, and an interport pattern. | 03-20-2014 |